[ARM] 5319/1: AT91: support AT91CAP9 revC CPUs
The AT91CAP9 revC CPU has a few differences over the previous,
revB CPU which was distributed in small quantities only (revA was
an internal Atmel product only).
This patch adds the detection routines to recognize the different
AT91CAP9 revisions (based on the PMC subsystem version number), and
uses them to:
- activate a workaround for the external interrupts levels
(on revB CPUs)
- set the UDPHS_BYPASS bit (on revB CPUs)
- set AT91_GPBR register address to the correct offset
(0xfffffd50 on revB, 0xfffffd60 on revC)
For debugging usage, the CPU revision can be found in /proc/cpuinfo
on the 'Revision' line.
This patch is extracted from Andrew Victor's -at91 patch (2.6.27-at91.patch)
where it has been tested for the last 6 months.
Signed-off-by: Stelian Pop <[email protected]>
Signed-off-by: Andrew Victor <[email protected]>
Signed-off-by: Russell King <[email protected]>
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 2e3f289..9561e33 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -23,6 +23,7 @@
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
+#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
@@ -102,10 +103,16 @@
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
+#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
+#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
+#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
+
+#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
+
#endif
