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authorJim Wilson <[email protected]>2018-12-27 15:25:49 -0800
committerMark Wielaard <[email protected]>2019-01-08 23:52:11 +0100
commit1dabad36ee28aa76b8cf14b6426b379cabee6def (patch)
tree5c45a0f2dbd30e53a288b2d31c7fa14aa73a2299 /backends/ChangeLog
parente8b9832af19e5975fb2a9dbe729eaba0373c781f (diff)
RISC-V: Improve riscv64 core file support.
This fixes two problems. The offset for x1 is changed from 1 to 8 because this is a byte offset not a register skip count. Support for reading the PC value is added. This requires changing the testsuite to match the new readelf output for coredumps. Signed-off-by: Jim Wilson <[email protected]>
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+2018-12-27 Jim Wilson <[email protected]>
+
+ * riscv_corenote.c (prstatus_regs): Change offset from 1 to 8.
+ (PRSTATUS_REGSET_ITEMS): New.
+
2018-11-06 Mark Wielaard <[email protected]>
* x86_64_symbol.c (x86_64_section_type_name): New function.