metroboy/docs/gateboy fails at master · aappleby/metroboy · GitHub

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need to trace clocks for RUPO_LYC_MATCH_LATCH
  inverting ROPO clock delays it even more

//----------
// PPU

ppu_sprite0_scx3_a.gb
  read happens waaaay after we hit hblank, wtf
  dmg pass, ags fail

ppu_sprite0_scx7_a.gb
  dmg pass, ags fail

//----------
// STAT

poweron_006_stat.gb / poweron_120_stat.gb
  dmg pass, ags fail
  cpu_data_latch is storing the 0 on the bus before oam lock drives it high.
  should be latching _after_ oam drives it high.

lcdon_to_stat2_a.gb
  dmg pass, ags fail

stat_write_glitch_l0_a.gb
  dmg pass, ags fail
stat_write_glitch_l0_b.gb
  dmg pass, ags fail
stat_write_glitch_l1_b.gb
  dmg pass, ags fail
stat_write_glitch_l1_c.gb
  dmg pass, ags fail

//----------
// OAM

oam_read_l0_d.gb
  dmg pass, ags pass
  PIN_OAM_OE goes low in AB
  CPU_OAM_RDn goes low in GH
  PIN_CPU_LATCH_EXT goes high in DE
  if CPU_RD was delayed we might be able to latch oam in HA

oam_read_l1_a.gb
  dmg pass, ags pass

oam_read_l1_f.gb
  dmg pass, ags pass

oam_write_l0_d.gb
  dmg pass, ags pass
  CPU_WRp goes low before rendering finishes

oam_write_l1_c.gb
  dmg pass, ags fail
  CPU_WRp pulse happens too far before the scan/render gap

lcdon_to_oam_unlock_d.gb
  dmg pass, ags pass
  should PIN_OAM_OE be low on EFGH?

poweron_006_oam.gb / poweron_120_oam.gb / poweron_234_oam.gb
  no gap between mode 1 and mode 2?
  checked gates and i seem to have verified all of them
  dmg pass, ags fail

//----------
// VRAM

poweron_026_vram.gb
  dmg pass, ags fail
poweron_140_vram.gb
  dmg pass, ags fail

//----------
// MEALYBUG

pass w/ sprite latch clock delayed 6 passes
  m3_lcdc_obj_size_change.gb
  m3_lcdc_obj_size_change_scx.gb

pass w pix delay 1 pass
  m3_lcdc_bg_en_change.gb
  m3_bgp_change.gb
  m3_lcdc_obj_en_change.gb
  m3_lcdc_obj_en_change_variant.gb

pass
  m3_lcdc_win_en_change_multiple_wx.gb -  image from mealybug wrong
  m3_bgp_change_sprites.gb
  m3_obp0_change.gb
  m3_lcdc_bg_map_change.gb
  m3_lcdc_tile_sel_change.gb
  m3_lcdc_tile_sel_win_change.gb
  m3_lcdc_win_en_change_multiple.gb
  m3_lcdc_win_map_change.gb
  m3_scx_low_3_bits.gb
  m3_window_timing.gb
  m3_window_timing_wx_0.gb
  m3_wx_4_change.gb
  m3_wx_4_change_sprites.gb
  m3_wx_5_change.gb
  m3_wx_6_change.gb