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Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux
Pull clock framework update from Michael Turquette: "The common clock framework changes for 3.9 are almost entirely fixes. None are dire enough to be Cc'd to stable which may be interpreted to mean that users of the framework are reaching stability. Lots of new adoption of this framework is via DeviceTree data and that comes through the respective architecture and platform trees instead of through the clk framework tree. Two new features are improved debugfs output and an improvement to how DT clocks are initialized by reusing a common method." * tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux: (25 commits) clk: sunxi: remove stale Makefile entry clk: vexpress: Use common of_clk_init() function clk: zynq: Use common of_clk_init() function clk: vt8500: Use common of_clk_init() function clk: highbank: Use common of_clk_init() function clk: sunxi: Use common of_clk_init() function clk: add common of_clk_init() function clk: Deduplicate exit code in clk_set_rate clk: beautify Makefile clk-divider: fix macros clk: prima2: enable dt-binding clkdev mapping clk: mxs: Index is always positive clk: max77686: Avoid double free at remove time clk: remove exported function from __init section clk: vt8500: Add support for WM8750/WM8850 PLL clocks clk: vt8500: Fix division-by-0 when requested rate=0 clk: vt8500: Fix device clock divisor calculations clk: vt8500: Fix error in PLL calculations on non-exact match. clk: max77686: Remove unnecessary NULL checking for container_of() clk: JSON debugfs clock tree summary ...
2 parents c6699b5 + fde8bc5 commit 10b6339

23 files changed

Lines changed: 527 additions & 276 deletions

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‎Documentation/devicetree/bindings/clock/prima2-clock.txt‎

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,73 @@
1+
* Clock bindings for CSR SiRFprimaII
2+
3+
Required properties:
4+
- compatible: Should be "sirf,prima2-clkc"
5+
- reg: Address and length of the register set
6+
- interrupts: Should contain clock controller interrupt
7+
- #clock-cells: Should be <1>
8+
9+
The clock consumer should specify the desired clock by having the clock
10+
ID in its "clocks" phandle cell. The following is a full list of prima2
11+
clocks and IDs.
12+
13+
Clock ID
14+
---------------------------
15+
rtc 0
16+
osc 1
17+
pll1 2
18+
pll2 3
19+
pll3 4
20+
mem 5
21+
sys 6
22+
security 7
23+
dsp 8
24+
gps 9
25+
mf 10
26+
io 11
27+
cpu 12
28+
uart0 13
29+
uart1 14
30+
uart2 15
31+
tsc 16
32+
i2c0 17
33+
i2c1 18
34+
spi0 19
35+
spi1 20
36+
pwmc 21
37+
efuse 22
38+
pulse 23
39+
dmac0 24
40+
dmac1 25
41+
nand 26
42+
audio 27
43+
usp0 28
44+
usp1 29
45+
usp2 30
46+
vip 31
47+
gfx 32
48+
mm 33
49+
lcd 34
50+
vpp 35
51+
mmc01 36
52+
mmc23 37
53+
mmc45 38
54+
usbpll 39
55+
usb0 40
56+
usb1 41
57+
58+
Examples:
59+
60+
clks: clock-controller@88000000 {
61+
compatible = "sirf,prima2-clkc";
62+
reg = <0x88000000 0x1000>;
63+
interrupts = <3>;
64+
#clock-cells = <1>;
65+
};
66+
67+
i2c0: i2c@b00e0000 {
68+
cell-index = <0>;
69+
compatible = "sirf,prima2-i2c";
70+
reg = <0xb00e0000 0x10000>;
71+
interrupts = <24>;
72+
clocks = <&clks 17>;
73+
};

‎arch/arm/boot/dts/prima2.dtsi‎

Lines changed: 30 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,10 +58,11 @@
5858
#size-cells = <1>;
5959
ranges = <0x88000000 0x88000000 0x40000>;
6060

61-
clock-controller@88000000 {
61+
clks: clock-controller@88000000 {
6262
compatible = "sirf,prima2-clkc";
6363
reg = <0x88000000 0x1000>;
6464
interrupts = <3>;
65+
#clock-cells = <1>;
6566
};
6667

6768
reset-controller@88010000 {
@@ -85,6 +86,7 @@
8586
compatible = "sirf,prima2-memc";
8687
reg = <0x90000000 0x10000>;
8788
interrupts = <27>;
89+
clocks = <&clks 5>;
8890
};
8991
};
9092

@@ -104,6 +106,7 @@
104106
compatible = "sirf,prima2-vpp";
105107
reg = <0x90020000 0x10000>;
106108
interrupts = <31>;
109+
clocks = <&clks 35>;
107110
};
108111
};
109112

@@ -117,6 +120,7 @@
117120
compatible = "powervr,sgx531";
118121
reg = <0x98000000 0x8000000>;
119122
interrupts = <6>;
123+
clocks = <&clks 32>;
120124
};
121125
};
122126

@@ -130,6 +134,7 @@
130134
compatible = "sirf,prima2-video-codec";
131135
reg = <0xa0000000 0x8000000>;
132136
interrupts = <5>;
137+
clocks = <&clks 33>;
133138
};
134139
};
135140

@@ -149,12 +154,14 @@
149154
compatible = "sirf,prima2-gps";
150155
reg = <0xa8010000 0x10000>;
151156
interrupts = <7>;
157+
clocks = <&clks 9>;
152158
};
153159

154160
dsp@a9000000 {
155161
compatible = "sirf,prima2-dsp";
156162
reg = <0xa9000000 0x1000000>;
157163
interrupts = <8>;
164+
clocks = <&clks 8>;
158165
};
159166
};
160167

@@ -174,107 +181,123 @@
174181
compatible = "sirf,prima2-nand";
175182
reg = <0xb0030000 0x10000>;
176183
interrupts = <41>;
184+
clocks = <&clks 26>;
177185
};
178186

179187
audio@b0040000 {
180188
compatible = "sirf,prima2-audio";
181189
reg = <0xb0040000 0x10000>;
182190
interrupts = <35>;
191+
clocks = <&clks 27>;
183192
};
184193

185194
uart0: uart@b0050000 {
186195
cell-index = <0>;
187196
compatible = "sirf,prima2-uart";
188197
reg = <0xb0050000 0x10000>;
189198
interrupts = <17>;
199+
clocks = <&clks 13>;
190200
};
191201

192202
uart1: uart@b0060000 {
193203
cell-index = <1>;
194204
compatible = "sirf,prima2-uart";
195205
reg = <0xb0060000 0x10000>;
196206
interrupts = <18>;
207+
clocks = <&clks 14>;
197208
};
198209

199210
uart2: uart@b0070000 {
200211
cell-index = <2>;
201212
compatible = "sirf,prima2-uart";
202213
reg = <0xb0070000 0x10000>;
203214
interrupts = <19>;
215+
clocks = <&clks 15>;
204216
};
205217

206218
usp0: usp@b0080000 {
207219
cell-index = <0>;
208220
compatible = "sirf,prima2-usp";
209221
reg = <0xb0080000 0x10000>;
210222
interrupts = <20>;
223+
clocks = <&clks 28>;
211224
};
212225

213226
usp1: usp@b0090000 {
214227
cell-index = <1>;
215228
compatible = "sirf,prima2-usp";
216229
reg = <0xb0090000 0x10000>;
217230
interrupts = <21>;
231+
clocks = <&clks 29>;
218232
};
219233

220234
usp2: usp@b00a0000 {
221235
cell-index = <2>;
222236
compatible = "sirf,prima2-usp";
223237
reg = <0xb00a0000 0x10000>;
224238
interrupts = <22>;
239+
clocks = <&clks 30>;
225240
};
226241

227242
dmac0: dma-controller@b00b0000 {
228243
cell-index = <0>;
229244
compatible = "sirf,prima2-dmac";
230245
reg = <0xb00b0000 0x10000>;
231246
interrupts = <12>;
247+
clocks = <&clks 24>;
232248
};
233249

234250
dmac1: dma-controller@b0160000 {
235251
cell-index = <1>;
236252
compatible = "sirf,prima2-dmac";
237253
reg = <0xb0160000 0x10000>;
238254
interrupts = <13>;
255+
clocks = <&clks 25>;
239256
};
240257

241258
vip@b00C0000 {
242259
compatible = "sirf,prima2-vip";
243260
reg = <0xb00C0000 0x10000>;
261+
clocks = <&clks 31>;
244262
};
245263

246264
spi0: spi@b00d0000 {
247265
cell-index = <0>;
248266
compatible = "sirf,prima2-spi";
249267
reg = <0xb00d0000 0x10000>;
250268
interrupts = <15>;
269+
clocks = <&clks 19>;
251270
};
252271

253272
spi1: spi@b0170000 {
254273
cell-index = <1>;
255274
compatible = "sirf,prima2-spi";
256275
reg = <0xb0170000 0x10000>;
257276
interrupts = <16>;
277+
clocks = <&clks 20>;
258278
};
259279

260280
i2c0: i2c@b00e0000 {
261281
cell-index = <0>;
262282
compatible = "sirf,prima2-i2c";
263283
reg = <0xb00e0000 0x10000>;
264284
interrupts = <24>;
285+
clocks = <&clks 17>;
265286
};
266287

267288
i2c1: i2c@b00f0000 {
268289
cell-index = <1>;
269290
compatible = "sirf,prima2-i2c";
270291
reg = <0xb00f0000 0x10000>;
271292
interrupts = <25>;
293+
clocks = <&clks 18>;
272294
};
273295

274296
tsc@b0110000 {
275297
compatible = "sirf,prima2-tsc";
276298
reg = <0xb0110000 0x10000>;
277299
interrupts = <33>;
300+
clocks = <&clks 16>;
278301
};
279302

280303
gpio: pinctrl@b0120000 {
@@ -507,17 +530,20 @@
507530
pwm@b0130000 {
508531
compatible = "sirf,prima2-pwm";
509532
reg = <0xb0130000 0x10000>;
533+
clocks = <&clks 21>;
510534
};
511535

512536
efusesys@b0140000 {
513537
compatible = "sirf,prima2-efuse";
514538
reg = <0xb0140000 0x10000>;
539+
clocks = <&clks 22>;
515540
};
516541

517542
pulsec@b0150000 {
518543
compatible = "sirf,prima2-pulsec";
519544
reg = <0xb0150000 0x10000>;
520545
interrupts = <48>;
546+
clocks = <&clks 23>;
521547
};
522548

523549
pci-iobg {
@@ -616,12 +642,14 @@
616642
compatible = "chipidea,ci13611a-prima2";
617643
reg = <0xb8000000 0x10000>;
618644
interrupts = <10>;
645+
clocks = <&clks 40>;
619646
};
620647

621648
usb1: usb@b00f0000 {
622649
compatible = "chipidea,ci13611a-prima2";
623650
reg = <0xb8010000 0x10000>;
624651
interrupts = <11>;
652+
clocks = <&clks 41>;
625653
};
626654

627655
sata@b00f0000 {
@@ -634,6 +662,7 @@
634662
compatible = "sirf,prima2-security";
635663
reg = <0xb8030000 0x10000>;
636664
interrupts = <42>;
665+
clocks = <&clks 7>;
637666
};
638667
};
639668
};

‎arch/arm/mach-highbank/core.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,6 @@
22
#define __HIGHBANK_CORE_H
33

44
extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
5-
extern void highbank_clocks_init(void);
65
extern void highbank_restart(char, const char *);
76
extern void __iomem *scu_base_addr;
87

‎arch/arm/mach-highbank/highbank.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@
2525
#include <linux/of_address.h>
2626
#include <linux/smp.h>
2727
#include <linux/amba/bus.h>
28+
#include <linux/clk-provider.h>
2829

2930
#include <asm/arch_timer.h>
3031
#include <asm/cacheflush.h>
@@ -117,7 +118,7 @@ static void __init highbank_timer_init(void)
117118
WARN_ON(!timer_base);
118119
irq = irq_of_parse_and_map(np, 0);
119120

120-
highbank_clocks_init();
121+
of_clk_init(NULL);
121122
lookup.clk = of_clk_get(np, 0);
122123
clkdev_add(&lookup);
123124

‎drivers/clk/Makefile‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,13 @@
11
# common clock types
22
obj-$(CONFIG_HAVE_CLK) += clk-devres.o
33
obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
4-
obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
5-
clk-mux.o clk-divider.o clk-fixed-factor.o
4+
obj-$(CONFIG_COMMON_CLK) += clk.o
5+
obj-$(CONFIG_COMMON_CLK) += clk-divider.o
6+
obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
7+
obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
8+
obj-$(CONFIG_COMMON_CLK) += clk-gate.o
9+
obj-$(CONFIG_COMMON_CLK) += clk-mux.o
10+
611
# SoCs specific
712
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
813
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
@@ -20,7 +25,6 @@ endif
2025
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
2126
obj-$(CONFIG_ARCH_U8500) += ux500/
2227
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
23-
obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o
2428
obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
2529

2630
# Chip specific

‎drivers/clk/clk-divider.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include <linux/io.h>
1717
#include <linux/err.h>
1818
#include <linux/string.h>
19+
#include <linux/log2.h>
1920

2021
/*
2122
* DOC: basic adjustable divider clock that cannot gate
@@ -29,8 +30,7 @@
2930

3031
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
3132

32-
#define div_mask(d) ((1 << (d->width)) - 1)
33-
#define is_power_of_two(i) !(i & ~i)
33+
#define div_mask(d) ((1 << ((d)->width)) - 1)
3434

3535
static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
3636
{
@@ -137,7 +137,7 @@ static bool _is_valid_table_div(const struct clk_div_table *table,
137137
static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
138138
{
139139
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
140-
return is_power_of_two(div);
140+
return is_power_of_2(div);
141141
if (divider->table)
142142
return _is_valid_table_div(divider->table, div);
143143
return true;

‎drivers/clk/clk-fixed-factor.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,11 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
2828
unsigned long parent_rate)
2929
{
3030
struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
31+
unsigned long long int rate;
3132

32-
return parent_rate * fix->mult / fix->div;
33+
rate = (unsigned long long int)parent_rate * fix->mult;
34+
do_div(rate, fix->div);
35+
return (unsigned long)rate;
3336
}
3437

3538
static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,

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