An open-source static random access memory (SRAM) compiler.

Physical Design of Mixed signal circuit that performs- "In Memory logic using 8TSRAM cells" using OPENFASOC.

Home Assistant integration for SRAM AXS components — battery status via BLE

𓃝 Khnum — the ram-headed god of memory. Zero-dependency, laptop-class open-source memory compiler: verified SRAM/RF/FIFO/ECC Verilog with formal proofs, FPGA BRAM inference, and 16GB-safe OpenROAD sky130 GDSII. pip install khnum-ram

This repository contains all the lecture slides, homeworks, Mid Terms, and the final project of the Computing Systems Architectures course by Prof. Azeez Bhavnagarwala, in Fall 2025 at NYU.

6T SRAM bitcell characterization in Cadence Virtuoso (DC + transient) with automated HSNM/RSNM extraction from butterfly CSVs (Python).

Predictive SRAM–DRAM–SSD memory fabric for low-cost AI inference, long-context KV cache tiering, MoE expert staging, and software-defined memory orchestration.

Design and analysis of 6T SRAM memory cells using LTspice. Analysis of noise margin, Vdd scaling and data retention voltage for design optimization.

Reproducible SRAM surrogate simulation benchmark with CPU/CUDA lanes, fidelity validation, and GPU portability architecture.

Exploratory AI infrastructure project modeling semantic KV-cache orchestration, memory tiering, and HBM/CXL movement tradeoffs for long-context LLM inference.

Plan self-attention tile sizes for FPGA and accelerator SRAM budgets.

HeteroCore component: SRAM hierarchy model and OpenRAM config generator

Python library / driver for MICROCHIP EERAM 47C04 / 47C16

8x8 6T SRAM design and simulation files for SKY130