Fig. 1

A trapped electron array on liquid Helium generated by the DC-bias electrodes and an rf-driving CPW-TLR. a The designed chip, wherein A1–A10 are the grounds, B1 and B2 are the CPW feed lines separated by a CPW-TLR (C), and D1–D8 are the DC-biased electrodes used to confine the x-direction motions of the trapped electrons, and the surface of the chip is covered by a layer of liquid Helium with the thickness \(h\sim 500\) nm [34]. Besides the trapped potentials generated by the voltage-biased electrodes, a standing wave along the y-direction is also excited by the CPW-TLR. Thus, a series of anharmonic potential wells are generated to trap a series of electrons on liquid Helium. b The parameters of a unit of the designed chip. The unit size is 12000 \(\mu \)m\(\times 100~\mu \)m, the thickness of the sapphire substrate is set as \(400~\mu \)m, and the widths of the TLR and the gaps are set as \(10~\mu \)m and \(5~\mu \)m, respectively