Denise Dewitz’s Post

Qt for MCUs 2.12.1 LTS is here with bug fixes and stability improvements. New updates include out-of-the-box support for Infineon PSOC Edge E84, STM32N6 AI microcontrollers, enhanced power-saving deep sleep for TRAVEO T2G, and Coco code coverage integration. Read the full blog for details and platform updates: https://lnkd.in/dA25T7-E

Qt for MCUs 2.12.1 LTS is here with bug fixes and stability improvements. New updates include out-of-the-box support for Infineon PSOC Edge E84, STM32N6 AI microcontrollers, enhanced power-saving deep sleep for TRAVEO T2G, and Coco code coverage integration. Read the full blog for details and platform updates: https://lnkd.in/etE3tm7Q

Qt for MCUs 2.12.1 LTS is here with bug fixes and stability improvements. New updates include out-of-the-box support for Infineon PSOC Edge E84, STM32N6 AI microcontrollers, enhanced power-saving deep sleep for TRAVEO T2G, and Coco code coverage integration. Read the full blog for details and platform updates: https://lnkd.in/eA82ex3p

Qt for MCUs 2.12.1 LTS is here with bug fixes and stability improvements. New updates include out-of-the-box support for Infineon PSOC Edge E84, STM32N6 AI microcontrollers, enhanced power-saving deep sleep for TRAVEO T2G, and Coco code coverage integration. Read the full blog for details and platform updates: https://lnkd.in/d6Ghh-U7

You're pushing camera frames through DDS. Your CPU is burning on serialization for no reason. ROS 2 has intra-process communication built in since Foxy. The idea is simple: if two nodes live in the same process, there's no reason to serialize the message, route it through DDS, and deserialize it on the other side. You pass the pointer. Zero-copy shared memory goes further — even across process boundaries on the same machine. ros2_shm_msgs by Zhensheng Lee (https://lnkd.in/ezn9xnM2) provides the message definitions and demos to set this up for images and point clouds — with measured results: ~80% reduction in transport time on image topics. On a 4K camera stream, the difference is measurable. DDS overhead is not free, and it compounds when you're running multiple high-frequency topics in parallel. Most teams never benchmark this. They add more cameras, notice the CPU struggling, and start optimizing the wrong layer. Have you measured DDS overhead on your heavy topics? What bandwidth are you running? I would love to hear about your experience!

Built a working microcontroller-to-microcontroller communication system using Arduino and ESP32. Designed and implemented a custom bit-level data transmission protocol where Arduino sends encoded characters over GPIO, and ESP32 reconstructs them using synchronized sampling (effectively a simplified serial communication system without UART libraries). On the receiver side, the decoded characters are mapped into Morse code representations, which are then visualized in real time using: LED feedback (blue = dot, green = dash) Buzzer signals (short beep = dot, long beep = dash) This is so much funnnnnnn! [GitHub repo link: https://lnkd.in/gMyWa73z]

𝗭𝘆𝗽𝗵𝗿𝗮 𝗥𝗲𝗹𝗲𝗮𝘀𝗲𝘀 𝗭𝗔𝗬𝗔𝟭-𝟴𝗕-𝗗𝗶𝗳𝗳𝘂𝘀𝗶𝗼𝗻-𝗣𝗿𝗲𝘃𝗶𝗲𝘄: 𝗧𝗵𝗲 𝗙𝗶𝗿𝘀𝘁 𝗠𝗼𝗘 𝗗𝗶𝗳𝗳𝘂𝘀𝗶𝗼𝗻 𝗠𝗼𝗱𝗲𝗹 𝗖𝗼𝗻𝘃𝗲𝗿𝘁𝗲𝗱 𝗙𝗿𝗼𝗺 𝗮𝗻 𝗔𝘂𝘁𝗼𝗿𝗲𝗴𝗿𝗲𝘀𝘀𝗶𝘃𝗲 𝗟𝗟𝗠 𝗪𝗶𝘁𝗵 𝗨𝗽 𝘁𝗼 𝟳.𝟳𝘅 𝗦𝗽𝗲𝗲𝗱𝘂𝗽 Zyphra's latest release shows that an autoregressive MoE model can be converted into a discrete diffusion model with no systematic loss in evaluation performance. ZAYA1-8B-Diffusion-Preview achieves up to 7.7x inference speedup over autoregression by shifting decoding from memory-bandwidth bound to compute-bound — a key advantage as modern GPUs continue scaling FLOPs faster than memory bandwidth. The post Zyphra Releases ZAYA1-8B-Diffusion-Preview: The First MoE Diffusion Model Converted From an Autoregressive LLM With Up to 7.7x Speedup appeared first on MarkTechPost. https://lnkd.in/eG2Uv-2q

Understanding Delta Cycles in SystemC (CPU & Temperature Models) As part of my MSc project on gem5–SystemC coupling, I explored delta cycles and execution ordering in SystemC through two small simulation models. I implemented: 🧠 CPU model ➡️ Instruction fetch/decode ➡️ Cache load/flush ➡️ Shared variable updates across processes 🌡️ Temperature model ➡️ CPU heat up/cool down ➡️ Clock boost/throttle ➡️ Concurrent state changes Key observations: ✔ wait(SC_ZERO_TIME) shifts execution to the next delta cycle ✔ Some processes see updated values only after a delta update ✔ Execution order is deterministic, not sequential like C++ 💡 Key insight: SystemC behavior is driven by event scheduling + delta cycles, not line-by-line execution. This is important for my work on Gem5–SystemC integration, where timing and synchronization are critical. #SystemC #DeltaCycle #Simulation #EmbeddedSystems #Cplusplus #gem5 #SystemDesign #HardwareModeling

Florence is very rainy this week - so here is one more reason to stay indoors and attend the keynote. :) I am happy to give a keynote tomorrow at ICPE — International Conference on Performance Engineering, where I will talk about the evolving GPU communication landscape and the performance tools my group have been developing: Snoopie, ucTrace, and a unnamed new tool that is still waiting for its awesome name. Looking forward to discussions on GPU-centric communication, performance analysis, and what it takes to make modern GPU systems more observable. #ICPE #HPC #GPU #PerformanceEngineering #Supercomputing #PerformanceTools

Currently building Vulcan OS. A minimal real-time operating system for the STM32H7 (Cortex-M7), written entirely in-house for edge ML workloads. No FreeRTOS. No STM32 HAL. No TFLite. Every byte is ours. The scheduler, memory allocator, DMA stack, peripheral drivers, tensor arena, and synchronization primitives are all being implemented from scratch in C and ARM assembly. The current target is the STM32H743ZI running at 480 MHz, with the tensor arena placed directly in DTCM RAM for low-latency ML workloads. Still heavily under development, but the long-term goal is a fully native embedded ML stack with complete control over timing, memory, and hardware behavior. Repo in the comments.