Rockchip RK3399 - USB调试

本文详细介绍了Rockchip RK3399的USB设备树配置、内核配置、测试设备以及模拟设备的过程。内容涵盖控制器配置、电源管理、内核选项设置、设备测试(如鼠标、键盘、摄像头、移动硬盘等)和模拟存储设备、声卡的实现,旨在帮助开发者进行有效的USB调试和功能验证。

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开发板 :NanoPC-T4开发板eMMC16GBLPDDR34GB
显示屏 :15.6英寸HDMI接口显示屏u-boot2023.04linux6.3
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一、设备树

设备树配置参考文档:

  • Documentation/devicetree/bindings/usb/generic-ehci.yaml; (USB控制器的通用属性配置说明)
  • Documentation/devicetree/bindings/usb/generic-ohci.yaml; (USB控制器的通用属性配置说明)
  • Documentation/devicetree/bindings/usb/generic-xhci.yaml; (USB控制器的通用属性配置说明)
  • Documentation/devicetree/bindings/usb/fcs,fusb302.yaml;
  • Documentation/devicetree/bindings/usb/rockchip,rk3399-dwc3.yaml;(适用于RK3399)
  • Documentation/devicetree/bindings/usb/usb-uhci.txt;
  • Documentation/devicetree/bindings/usb/usb-xhci.yaml;
  • Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt;
  • Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml;
  • Documentation/devicetree/bindings/phy/rockchip-usb-phy.yaml;
1.1 USB2.0 Host Type-A

NanoPC-T4开发板支持两个USB2.0 Host Type-A接口,对应的USB控制器为USB2.0 HOST(EHCI&OHCI)、对应的USB PHYUSB2.0 HOST PHY

因此对应的设备树配置,包括USB2.0 HOST(EHCI&OHCI)控制器设备树配置和USB2.0 HOST PHY设备树配置。

1.1.1 控制器配置

(1) USB2.0 HOST0控制器设备节点usb_host0_ehciusb_host0_ohci定义在arch/arm64/boot/dts/rockchip/rk3399.dtsi

usb_host0_ehci: usb@fe380000 {
		compatible = "generic-ehci";
		reg = <0x0 0xfe380000 0x0 0x20000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
				 <&u2phy0>;
		phys = <&u2phy0_host>;
		phy-names = "usb";
		status = "disabled";
};

usb_host0_ohci: usb@fe3a0000 {
		compatible = "generic-ohci";
		reg = <0x0 0xfe3a0000 0x0 0x20000>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
				 <&u2phy0>;
		phys = <&u2phy0_host>;
		phy-names = "usb";
		status = "disabled";
};

USB控制器设备节点中,通过phys属性关联对应的USB PHY

phys = <&u2phy0_host>;

这表明这两个USB控制器都用了u2phy0_host这个USB PHY.

这两个USB控制器就是我们之前介绍的是EHCIOHCIOHCI支持USB1.0USB1.1EHCI支持USB2.0

(2) USB2.0 HOST1控制器设备节点usb_host1_ehciusb_host1_ohci定义在arch/arm64/boot/dts/rockchip/rk3399.dtsi

usb_host1_ehci: usb@fe3c0000 {
		compatible = "generic-ehci";
		reg = <0x0 0xfe3c0000 0x0 0x20000>;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
				 <&u2phy1>;
		phys = <&u2phy1_host>;
		phy-names = "usb";
		status = "disabled";
};

usb_host1_ohci: usb@fe3e0000 {
		compatible = "generic-ohci";
		reg = <0x0 0xfe3e0000 0x0 0x20000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
				 <&u2phy1>;
		phys = <&u2phy1_host>;
		phy-names = "usb";
		status = "disabled";
};
1.1.2 PHY配置

(1) USB2.0 HOST PHY0设备节点u2phy0_host定义在arch/arm64/boot/dts/rockchip/rk3399.dtsi

u2phy0: usb2phy@e450 {
		compatible = "rockchip,rk3399-usb2phy";
		reg = <0xe450 0x10>;
		clocks = <&cru SCLK_USB2PHY0_REF>;
		clock-names = "phyclk";
		#clock-cells = <0>;
		clock-output-names = "clk_usbphy0_480m";
		status = "disabled";

		u2phy0_host: host-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "linestate";
				status = "disabled";
		};

		u2phy0_otg: otg-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
							 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
							 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "otg-bvalid", "otg-id",
								  "linestate";
				status = "disabled";
		};
};

(2) USB2.0 HOST PHY1设备节点u2phy1_host定义在arch/arm64/boot/dts/rockchip/rk3399.dtsi

u2phy1: usb2phy@e460 {
		compatible = "rockchip,rk3399-usb2phy";
		reg = <0xe460 0x10>;
		clocks = <&cru SCLK_USB2PHY1_REF>;
		clock-names = "phyclk";
		#clock-cells = <0>;
		clock-output-names = "clk_usbphy1_480m";
		status = "disabled";

		u2phy1_host: host-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "linestate";
				status = "disabled";
		};

		u2phy1_otg: otg-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
							 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
							 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "otg-bvalid", "otg-id",
								  "linestate";
				status = "disabled";
		};
};
1.1.3 电源配置

(1) USB2.0 PHY芯片三路电源依次为VCCA0V9_S3VCCA1V8_S3VCC3V3_S3

VCCA0V9_S3VCCA1V8_S3这两路由PMIC_SLEEP_H(连接RK3399GPIO1_A5/AP_PWROFF,这个应该是处理的睡眠引脚,处理器工作时电源有效)引脚控制的;

VCC3V3_S3RK808电源管理芯片第7号引脚VSWOUT提供,因此需要配置其电源输出为3.3V

arch/arm64/boot/dts/rockchip/rk3399-evb.dts配置vcc3v3_s3设备节点;

&i2c0 {
    ...... 

    rk808: pmic@1b {
		......

        regulators {
           
		    ......
			
            vcc3v3_s3: SWITCH_REG1 {
                regulator-always-on;
                regulator-boot-on;
                regulator-name = "vcc3v3_s3";

                regulator-state-mem {
                    regulator-off-in-suspend;
                };
            };
			
			......

        };
    };
};

完整的rk808设备节点配置参考:rk808驱动配置

(2) USB2.0 Host Type-A接口电源VCC5V0_HOST0RT9724GQW提供的,其输入端为VCC5V0_SYS

arch/arm64/boot/dts/rockchip/rk3399-evb.dts配置vcc5v0_host

vcc5v0_sys: vcc5v0-sys {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
};

vcc5v0_host: vcc5v0-host-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_host";
		regulator-always-on;
		regulator-boot-on;	
		vin-supply = <&vcc5v0_sys>;
};
1.1.4 使能

下面介绍的都是配置在arch/arm64/boot/dts/rockchip/rk3399-evb.dts文件。

(1) 为了同时支持USB1.0USB1.1USB2.0,就需要同时用到EHCIOHCI,因此需要把这两个USB控制器都打开:

&usb_host0_ehci {
        status = "okay";
};

&usb_host0_ohci {
        status = "okay";
};

&usb_host1_ehci {
        status = "okay";
};

&usb_host1_ohci {
        status = "okay";
};

(2) 使能USB2.0 HOST PHY0,同时配置USB2.0 HOST PHY0 phy-supply属性,用于控制USB电源VBUS

&u2phy0 {
        status = "okay";
};

&u2phy0_host {
        phy-supply = <&vcc5v0_host>;
        status = "okay";
};

(3) 使能USB2.0 HOST PHY1,同时配置USB2.0 HOST PHY1 phy-supply属性,用于控制USB电源VBUS

&u2phy1 {
        status = "okay";
};

&u2phy1_host {
        phy-supply = <&vcc5v0_host>;
        status = "okay";
};
1.2 USB3.0 Host Type-A

NanoPC-T4开发板支持1个USB3.0 Host Type-A接口,对应的USB控制器为USB3.0/2.0 OTG1(DWC3/xHCI)、对应的USB PHYUSB3.0 Type-C PHY1USB2.0 OTG PHY1

因此对应的设备树配置,包括USB3.0/2.0 OTG1(DWC3/xHCI)控制器设备树配置和USB3.0 Type-C PHY1USB2.0 OTG PHY1设备树配置。

1.2.1 控制器配置

(1) USB3.0/2.0 OTG1(DWC3/xHCI)控制器设备节点usbdrd3_1,定义在arch/arm64/boot/dts/rockchip/rk3399.dtsi

usbdrd3_1: usb@fe900000 {
		compatible = "rockchip,rk3399-dwc3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
				 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
				 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
		clock-names = "ref_clk", "suspend_clk",
					  "bus_clk", "aclk_usb3_rksoc_axi_perf",
					  "aclk_usb3", "grf_clk";
		resets = <&cru SRST_A_USB3_OTG1>;
		reset-names = "usb3-otg";
		status = "disabled";
		usbdrd_dwc3_1: usb@fe900000 {
				compatible = "snps,dwc3";
				reg = <0x0 0xfe900000 0x0 0x100000>;
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
						 <&cru SCLK_USB3OTG1_SUSPEND>;
				clock-names = "ref", "bus_early", "suspend";
				dr_mode = "otg";
				phys = <&u2phy1_otg>, <&tcphy1_usb3>;
				phy-names = "usb2-phy", "usb3-phy";
				phy_type = "utmi_wide";
				snps,dis_enblslpm_quirk;
				snps,dis-u2-freeclk-exists-quirk;
				snps,dis_u2_susphy_quirk;
				snps,dis-del-phy-power-chg-quirk;
				snps,dis-tx-ipgap-linecheck-quirk;
				power-domains = <&power RK3399_PD_USB3>;
				status = "disabled";
		};
};
1.2.2 PHY配置

(1) USB3.0 Type-C PHY1设备节点tcphy1_usb3,定义在arch/arm64/boot/dts/rockchip/rk3399.dtsi

tcphy1: phy@ff800000 {
		compatible = "rockchip,rk3399-typec-phy";
		reg = <0x0 0xff800000 0x0 0x40000>;
		clocks = <&cru SCLK_UPHY1_TCPDCORE>,
				 <&cru SCLK_UPHY1_TCPDPHY_REF>;
		clock-names = "tcpdcore", "tcpdphy-ref";
		assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
		assigned-clock-rates = <50000000>;
		power-domains = <&power RK3399_PD_TCPD1>;
		resets = <&cru SRST_UPHY1>,
				 <&cru SRST_UPHY1_PIPE_L00>,
				 <&cru SRST_P_UPHY1_TCPHY>;
		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
		rockchip,grf = <&grf>;
		status = "disabled";

		tcphy1_dp: dp-port {
				#phy-cells = <0>;
		};

		tcphy1_usb3: usb3-port {
				#phy-cells = <0>;
		};
};

(2) USB2.0 OTG PHY1设备节点u2phy1_otg,定义在arch/arm64/boot/dts/rockchip/rk3399.dtsi

u2phy1: usb2phy@e460 {
		compatible = "rockchip,rk3399-usb2phy";
		reg = <0xe460 0x10>;
		clocks = <&cru SCLK_USB2PHY1_REF>;
		clock-names = "phyclk";
		#clock-cells = <0>;
		clock-output-names = "clk_usbphy1_480m";
		status = "disabled";

		u2phy1_host: host-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "linestate";
				status = "disabled";
		};

		u2phy1_otg: otg-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
							 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
							 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "otg-bvalid", "otg-id",
								  "linestate";
				status = "disabled";
		};
};
1.2.3 电源配置

(1) USB2.0 PHY1芯片三路电源依次为VCCA0V9_S3VCCA1V8_S3VCC3V3_S3, 这个配置上面已经介绍了,不再重复介绍。

(2) USB3.0 Type-C PHY1芯片三路电源和USB2.0 PHY1芯片三路电源一样。

(3) USB3.0 Host Type-A接口电源VCC5V0_HOST2RT9724GQW提供的,其输入端为VCC5V0_SYS

arch/arm64/boot/dts/rockchip/rk3399-evb.dts配置vcc5v2_host

vcc5v0_sys: vcc5v0-sys {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
};

vcc5v2_host: vcc5v2-host-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v2_host";
		regulator-always-on;
		regulator-boot-on;	
		vin-supply = <&vcc5v0_sys>;
};
1.2.4 使能

下面介绍的都是配置在arch/arm64/boot/dts/rockchip/rk3399-evb.dts文件。

(1) 使能usbdrd3_1

/* Configurate and Enable USB3.0/2.0 OTG Controller */
&usbdrd3_1 {
	status = "okay";
};

&usbdrd_dwc3_1 {
	/* 配置dr_mode为host,表示只支持Host only mode */
	dr_mode = "host";
	status = "okay";
};

(2) 使能tcphy1_usb3

/* Enable USB3.0 PHY */
&tcphy1 {
	status = "okay";
};

&tcphy1_usb3{
	status = "okay";
};

(3) 使能u2phy1_otg,同时配置USB2.0 OTG PHY1 phy-supply属性,用于控制USB电源VBUS

/* Enable USB2.0 PHY */
&u2phy1 {
   status = "okay";
};

&u2phy1_otg {
	phy-supply = <&vcc5v2_host>;
	status = "okay";
};
1.2.5 总结

USB3.0 Host Type-A接口设备树配置的注意点如下:

  • 对应的fusb节点不要配置,因为USB3.0 Host Type-A接口不需要fusb302芯片;
  • 对应的USB控制器子节点(usbdrd_dwc3)和PHY的节点(tcphyu2phy)都要删除extcon属性;
  • 对应的USB控制器子节点(usbdrd_dwc3)的dr_mode属性要配置为host
1.3 USB3.0 Type-C

NanoPC-T4开发板支持1个USB3.0 Type-C接口,对应的USB控制器为USB3.0/2.0 OTG0(DWC3/xHCI)、对应的USB PHYUSB3.0 Type-C PHY0USB2.0 OTG PHY0

因此对应的设备树配置,包括USB3.0/2.0 OTG0(DWC3/xHCI)控制器设备树配置和USB3.0 Type-C PHY0USB2.0 OTG PHY0设备树配置。

1.3.1 控制器配置

(1) USB3.0/2.0 OTG0(DWC3/xHCI)控制器设备节点usbdrd3_0,定义在arch/arm64/boot/dts/rockchip/rk3399.dtsi

usbdrd3_0: usb@fe800000 {
		compatible = "rockchip,rk3399-dwc3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
				 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
				 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
		clock-names = "ref_clk", "suspend_clk",
					  "bus_clk", "aclk_usb3_rksoc_axi_perf",
					  "aclk_usb3", "grf_clk";
		resets = <&cru SRST_A_USB3_OTG0>;
		reset-names = "usb3-otg";
		status = "disabled";
		usbdrd_dwc3_0: usb@fe800000 {
				compatible = "snps,dwc3";
				reg = <0x0 0xfe800000 0x0 0x100000>;
				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
						 <&cru SCLK_USB3OTG0_SUSPEND>;
				clock-names = "ref", "bus_early", "suspend";
				dr_mode = "otg";
				phys = <&u2phy0_otg>, <&tcphy0_usb3>;
				phy-names = "usb2-phy", "usb3-phy";
				phy_type = "utmi_wide";
				snps,dis_enblslpm_quirk;
				snps,dis-u2-freeclk-exists-quirk;
				snps,dis_u2_susphy_quirk;
				snps,dis-del-phy-power-chg-quirk;
				snps,dis-tx-ipgap-linecheck-quirk;
				power-domains = <&power RK3399_PD_USB3>;
				status = "disabled";
		};
};
1.3.2 PHY配置

(1) USB3.0 Type-C PHY0设备节点tcphy0_usb3,定义在arch/arm64/boot/dts/rockchip/rk3399.dtsi

tcphy0: phy@ff7c0000 {
		compatible = "rockchip,rk3399-typec-phy";
		reg = <0x0 0xff7c0000 0x0 0x40000>;
		clocks = <&cru SCLK_UPHY0_TCPDCORE>,
				 <&cru SCLK_UPHY0_TCPDPHY_REF>;
		clock-names = "tcpdcore", "tcpdphy-ref";
		assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
		assigned-clock-rates = <50000000>;
		power-domains = <&power RK3399_PD_TCPD0>;
		resets = <&cru SRST_UPHY0>,
				 <&cru SRST_UPHY0_PIPE_L00>,
				 <&cru SRST_P_UPHY0_TCPHY>;
		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
		rockchip,grf = <&grf>;
		status = "disabled";

		tcphy0_dp: dp-port {
				#phy-cells = <0>;
		};

		tcphy0_usb3: usb3-port {
				#phy-cells = <0>;
		};
};

(2) USB2.0 OTG PHY0设备节点u2phy0_otg,定义在arch/arm64/boot/dts/rockchip/rk3399.dtsi

u2phy0: usb2phy@e450 {
		compatible = "rockchip,rk3399-usb2phy";
		reg = <0xe450 0x10>;
		clocks = <&cru SCLK_USB2PHY0_REF>;
		clock-names = "phyclk";
		#clock-cells = <0>;
		clock-output-names = "clk_usbphy0_480m";
		status = "disabled";

		u2phy0_host: host-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "linestate";
				status = "disabled";
		};

		u2phy0_otg: otg-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
							 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
							 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "otg-bvalid", "otg-id",
								  "linestate";
				status = "disabled";
		};
};
1.3.3 电源配置

(1) USB2.0 PHY0芯片三路电源依次为VCCA0V9_S3VCCA1V8_S3VCC3V3_S3, 这个配置上面已经介绍了,不再重复介绍。

(2) USB3.0 Type-C PHY0芯片三路电源和USB2.0 PHY0芯片三路电源一样。

(3) USB3.0 Type-C接口电源VBUS_TYPECRT9724GQW提供的,其输入端为VCC5V0_SYS。由GPIO4_D2引脚使能,高电平有效;

arch/arm64/boot/dts/rockchip/rk3399-evb.dts配置vbus_typec

vcc5v0_sys: vcc5v0-sys {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
};

vbus_typec: vbus-typec {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&vbus_typec_en>;
		regulator-name = "vbus_typec";
		vin-supply = <&vcc5v0_sys>;
};

由于vbus_typec节点配置了default状态对应的引脚配置节点为vbus_typec_en,因此需要在pinctrl节点下增加引脚配置节点vbus_typec_en,这个节点在fusb配置中介绍。

1.3.4 fusb302配置

arch/arm64/boot/dts/rockchip/rk3399-evb.dts配置:

&i2c4 {
        clock-frequency = <400000>;
        i2c-scl-rising-time-ns = <160>;
        i2c-scl-falling-time-ns = <30>;
        status = "okay";

        fusb0: typec-portc@22 {
                compatible = "fcs,fusb302";
                reg = <0x22>;
                interrupt-parent = <&gpio1>;
                interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
                pinctrl-names = "default";
                pinctrl-0 = <&fusb0_int>;
                vbus-supply = <&vbus_typec>;
	
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