因为
如果是减1的话是会少减1的 因为piel_x会延迟
`timescale 1ns / 1ps
module vga(
//系统侧
input wire clk_sys ,
input wire rst_n ,
input wire clk ,//在顶层例化的pll产生的
input wire locked ,
//物理侧
output wire [23:0] rgb ,
output wire vsync ,
output wire hsync ,
output wire video_de
);
parameter H_SYNC = 11'd40 ; //行同步
parameter H_BACK = 11'd220 ; //行显示后沿
parameter H_LEFT = 11'd0 ;
parameter H_DISP = 11'd1280 ; //行有效数据
parameter H_RIGHT = 11'd0 ;
parameter H_FRONT = 11'd110 ; //行显示前沿
parameter H_TOTAL = 11'd1650 ; //行扫描周期
parameter V_SYNC = 11'd5 ; //场同步
parameter V_BACK = 11'd20 ; //场显示后沿
parameter V_TOP = 11'd0 ;
parameter V_DISP = 11'd720 ; //场有效数据
parameter V_BOTTOM = 11'd0 ;
parameter V_FRONT = 11'd5 ; //场显示前沿
parameter V_TOTAL = 11'd750 ; //场扫描周期
//
localparam WHITE = 24'b11111111_11111111_11111111; //RGB888 白色
localparam BLACK = 24'b00000000_00000000_00000000; //RGB888 黑色
localparam RED = 24'b11111111_00001100_00000000; //RGB888 红色
localparam GREEN = 24'b00000000_11111111_00000000; //RGB888 绿色
localparam BLUE = 24'b00000000_00000000_11111111; //RGB888 蓝色
//
wire rst ;
wire ena ;
wire [23:0] douta ;
wire [13 : 0] addra ; //0~9999
reg [23:0] data ;
//
reg [11:0] pixel_x ;
reg [11:0] pixel_y ;
reg data_req ;//图形有效的时候
reg [11:0] cunt ; //行扫描周期计数
reg [11:0] cunt_b ; //列扫描周期计数
reg video_en ;
assign hsync=(cunt<H_SYNC) ?1'b1:1'b0;
assign vsync=(cunt_b<V_SYNC)?1'b1:1'b0;
assign rst =(rst_n==1&&locked==1)?1'b1:1'b0; //待PLL生成的clk稳定的时候 locked拉高
assign video_de=video_en;
assign rgb=(video_en==1'b1)?douta:24'b0;
always @(posedge clk or negedge rst) begin
if(!rst)
data_req<=1'b0;
else if((cunt>=hsync+H_BACK-2'd2&&cunt<hsync+H_BACK+H_DISP-2'd2)&&((cunt_b>=vsync+V_BACK)&&(cunt_b<vsync+V_BACK+V_DISP)))
data_req<=1'b1;
else
data_req<=1'b0;
end
always @(posedge clk or negedge rst) begin
if(!rst)
video_en<=0;
else if(data_req==1)
video_en<=1'b1;
else
video_en<=1'b0;
end
always @(posedge clk or negedge rst) begin
if(!rst)
pixel_x<=1'b0;
else if(data_req==1)
pixel_x<=(cunt-hsync-H_BACK+2);
else
pixel_x<=12'd0;
end
always @(posedge clk or negedge rst) begin
if(!rst)
pixel_y<=1'b0;
else if((cunt_b>=vsync+V_BACK)&&(cunt_b<vsync+V_BACK+V_DISP))
pixel_y<=(cunt_b-vsync-V_BACK);
else
pixel_y<=12'd0;
end
always @(posedge clk or negedge rst) begin
if(!rst)
data<=24'b0;
else if(pixel_x>=0&&pixel_x<H_DISP/5)
data<=WHITE;
else if(pixel_x>=H_DISP/5&&pixel_x<H_DISP/5*2)
data<=BLUE;
else if(pixel_x>=H_DISP/5*2&&pixel_x<H_DISP/5*3)
data<=GREEN;
else if(pixel_x>=H_DISP/5*3&&pixel_x<H_DISP/5*4)
data<=RED;
else
data<=BLACK;
end
//行扫描周期计数器
always @(posedge clk or negedge rst) begin
if(!rst)
cunt<=1'b0;
else begin
if(cunt==H_TOTAL-1)
cunt<=1'b0;
else
cunt<=cunt+1'b1;
end
end
//场扫描周期
always @(posedge clk ) begin
if(!rst)
cunt_b<=1'b0;
else begin
if(cunt_b==V_TOTAL-1&&cunt==H_TOTAL-1)
cunt_b<=1'b0;
else begin
if(cunt==H_TOTAL-1)
cunt_b<=cunt_b+1;
else
cunt_b<=cunt_b;
end
end
end
assign ena =1'b1;
//地址
assign addra =pixel_x%100+(pixel_y%100)*100;
blk_mem_gen_0 your_instance_name (
.clka(clk), // input wire clka
.ena(ena), // input wire ena
.addra(addra), // input wire [13 : 0] addra
.douta(douta) // output wire [23 : 0] douta
);
endmodule
正确的代码下的波形图