AD9172-FMC-EBZ（HMC7044+AD9172）调试记录

AD9172-FMC-EBZ 主要由HMC7044和AD9172构成，其中HMC7044负责提供204B所需要的时钟，AD9172完成和发送端204B数据通信并进行DAC转换输出，接下来分别讲述HMC7044和AD9172配置过程。

1. HMC7044调试

HMC7044配置，到ADI官网下载HMC7044 datasheet，官方配置小软件

HMC7044最关键的是需要设置合理的寄存器参数使得PLL1和PLL2锁定。

The function of PLL1 is to lock a clean VCXO to the average frequency of one of  these references and feed it to PLL2 to generate a high quality clock for local use.

OSCIN开发板提供的122.88M时钟，HMC7044支持CLKIN0~3四路时钟输入，可以通过寄存器0X0014配置输入时钟优先级，CLKIN0~3均有相应的使能寄存器0X000A~0X000D，开发板中CLKin0接到板内122.88M晶振，也可以通过CLKIN1通过外部时钟接入，配置合理的R0~R3(0X001C~0X001D)，R1 divider和N1 divider即可完成PLL1锁定，配置合理的doubler (0X0032),R2 divider和N2 divider即可完成PLL1锁定

{16'h0033 , 8'h10  };   //REG_PLL2_R_LSB
{16'h0034 , 8'h00  };	//REG_PLL2_R_MSB
{16'h0035 , 8'h90  };	//REG_PLL2_N_LSB  
{16'h0036 , 8'h01  };	//REG_PLL2_N_MSB
{16'h0032 , 8'h01  };	//
{16'h001A , 8'h06  };   //PLL1 Charge Pump Control, [3:0] PLL1 CP Current[3:0] PLL1 charge pump current/*Program PLL1.*/
{16'h0028 , 8'h0F  };   //PLL1 Lock Detect Timer[4:0]
{16'h0020 , 8'h04  };   //OSCIN/OSCIN Input Prescaler[7:0]
{16'h0021 , 8'h05  };   //REG_PLL1_R_LSB
{16'h0022 , 8'h00  };   //REG_PLL1_R_MSB
{16'h0026 , 8'h10  };   //REG_PLL1_N_LSB
{16'h0027 , 8'h00  };	  //REG_PLL1_N_MSB
{16'h0014 , 8'hE1  };   //PLL1 Reference Priority Control
{16'h0029 , 8'h05  };	  //PLL1 Reference Switching Control
{16'h001C , 8'h04  }; 
{16'h001D , 8'h05  };	
{16'h001E , 8'h04  }; 
{16'h001F , 8'h04  };	

配置GPO2用于指示PLL1和PLL2锁定情况，PLL1和PLL2都锁定时板子上DS5会熄灭

{16'h0051 , 8'h37  };   //REG_GPO2_CTRL PLL1 and PLL2 lock detect is locked

接下来配置HMC7044输出，可以用小工具配置需要输出的通道并导出寄存器值

开发板需要配置channel2,3,12,13分别用作AD9172的CLKIN和SYSREF，参考配置如下：

        10'd  52: lut_data <= {16'h00DC , 8'h73  };   ///* Program the output channel 2 */ F3
		10'd  53: lut_data <= {16'h00DD , 8'h08  };   //12-bit channel 2 divider setpoint LSB 122.88
		10'd  54: lut_data <= {16'h00DE , 8'h00  };   //12-bit channel 2 divider setpoint MSB.
		10'd  55: lut_data <= {16'h00DF , 8'h00  };	  //
		10'd  56: lut_data <= {16'h00E0 , 8'h00  };	  //
		10'd  57: lut_data <= {16'h00E1 , 8'h00  };   //
		10'd  58: lut_data <= {16'h00E2 , 8'h00  };   //
		10'd  59: lut_data <= {16'h00E3 , 8'h00  };   //
		10'd  60: lut_data <= {16'h00E4 , 8'h13  };	  //01
		10'd  61: lut_data <= {16'h00E6 , 8'h71  };	  ///* Program the output channel 3 */
		10'd  62: lut_data <= {16'h00E7 , 8'h00  };   //12-bit channel 3 divider setpoint LSB 122.88*21/7/32=11.52
		10'd  63: lut_data <= {16'h00E8 , 8'h02  };   //12-bit channel 3 divider setpoint MSB.
		10'd  64: lut_data <= {16'h00E9 , 8'h00  };   //
		10'd  65: lut_data <= {16'h00EA , 8'h00  };	  //
		10'd  66: lut_data <= {16'h00EB , 8'h00  };	  //
		10'd  67: lut_data <= {16'h00EC , 8'h00  };   //
		10'd  68: lut_data <= {16'h00ED , 8'h00  };   //
		10'd  69: lut_data <= {16'h00EE , 8'h11  };   //
		10'd  70: lut_data <= {16'h0140 , 8'h71  };	  ///* Program the output channel 12 */
		10'd  71: lut_data <= {16'h0141 , 8'h08  };	  //12-bit channel 12 divider setpoint LSB
		10'd  72: lut_data <= {16'h0142 , 8'h00  };   //12-bit channel 12 divider setpoint MSB.
		10'd  73: lut_data <= {16'h0143 , 8'h00  };   //
		10'd  74: lut_data <= {16'h0144 , 8'h00  };   //
		10'd  75: lut_data <= {16'h0145 , 8'h00  };	  //
		10'd  76: lut_data <= {16'h0146 , 8'h00  };	  //
		10'd  77: lut_data <= {16'h0147 , 8'h00  };   //
		10'd  78: lut_data <= {16'h0148 , 8'h11  };   //
		10'd  79: lut_data <= {16'h014A , 8'h71  };   ///* Program the output channel 13 */
		10'd  80: lut_data <= {16'h014B , 8'h00  };	  //12-bit channel 13 divider setpoint LSB
		10'd  81: lut_data <= {16'h014C , 8'h02  };	  //12-bit channel 13 divider setpoint MSB.
		10'd  82: lut_data <= {16'h014D , 8'h00  };   //
		10'd  83: lut_data <= {16'h014E , 8'h00  };   //
		10'd  84: lut_data <= {16'h014F , 8'h00  };   //
		10'd  85: lut_data <= {16'h0150 , 8'h00  };	  //
		10'd  86: lut_data <= {16'h0151 , 8'h00  };	  //
		10'd  87: lut_data <= {16'h0152 , 8'h11  };   //

2. AD9172配置

AD9172配置可以借助官网ACE+DPG软件，配置对应204B MODE和相应DAC PLL参数并导出相应寄存器配置。

配置主要过程参考AD9172 datasheet START-UP SEQUENCE章节，按照table49~58要求完成配置，注意表格中要求的等待时间也要严格遵守，同时检查表格要求的检查的寄存器状态；

配置完成后检查CGS, Frame Sync, Checksum, and ILAS对应的寄存器状态0X470~0X473状态都为0XF时说明配置正确。