tiny4412 uboot 2020.10版本移植（三）——uboot初步启动

最新推荐文章于 2025-06-11 11:41:05 发布

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最新推荐文章于 2025-06-11 11:41:05 发布

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分类专栏： uboot 文章标签： uboot u-boot bootloader samsung 三星

本文链接：https://blog.csdn.net/lgc1990/article/details/109160426

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本文详细介绍了如何将2020.10版的uboot移植到Tiny4412核心板上，涉及了添加交叉编译器信息、配置菜单、创建板级文件、修改设备树文件、时钟初始化和 soc 级别的修改。最后，作者提到了还需要进行更多的工作以完善uboot的功能，如UART调试、eMMC启动和USB功能等。

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这篇文章主要描述如何把2020.10版本的原生uboot在tiny4412核心板(1412版)上启动起来，而不关注一些细节问题。(文章结尾有下载源代码的链接)

该uboot的下一个修改版——能从SD卡或者eMMC启动内核，请参见《tiny4412 uboot 2020.10版本移植（四）——uboot修改支持sd卡、eMMC引导内核及其他一些杂项设置》

一、添加交叉编译器信息到Makefile

打开uboot源代码根目录下的Makefile,在开头添加如下：

ARCH = arm

CROSS_COMPILE = ~/WDC250GBHD/toolchain/gcc-arm-none-eabi-9-2020-q2-update/bin/arm-none-eabi-

CROSS_COMPILE是自己交叉编译器所在的路径。（有关编译器的下载版本参见《tiny4412 uboot 2020.10版本移植系列（一）——交叉编译器的选择》）

执行make menuconfig,可以发现编译器已经修改为添加进去的编译器。

二、make menuconfig找到合适的参考板子并进行板级文件的创建

2.1. uboot代码根目录下执行make menuconfig，如下进行配置：

Architecture select选择ARM architecture

ARM架构下面可以选择具体的芯片，具体的板子。如下：

ARM architecture --->

Target select (Samsung EXYNOS) --->

[*] EXYNOS architecture type select (Exynos4 SoC family) --->

EXYNOS4 board select (Exynos4412 Origen board) --->

EXYNOS4 board select这里选Exynos4412 Origen board，通过比较，可以使用SPL功能，是一个比较符合tiny4412板子的选项。但这里我打算自己新建一个选项，让tiny4412板子的配置独立开来。

根据这个信息，我们可以进行下面的修改：

------------------------------------------------------

2.2. 修改arch/arm/mach-exynos/Kconfig文件

@@ -67,6 +67,10 @@
 	bool "Exynos4412 Origen board"
 	select SUPPORT_SPL
 
+config TARGET_TINY4412
+	bool "Exynos4412 Tiny4412 board"
+	select SUPPORT_SPL
+
 config TARGET_TRATS2
 	bool "Exynos4412 Trat2 board"
 
@@ -161,6 +165,7 @@
 source "board/samsung/trats/Kconfig"
 source "board/samsung/universal_c210/Kconfig"
 source "board/samsung/origen/Kconfig"
+source "board/samsung/tiny4412/Kconfig"
 source "board/samsung/trats2/Kconfig"
 source "board/samsung/odroid/Kconfig"
 source "board/samsung/arndale/Kconfig"

---------------------------------------------------------

2.3. 创建tiny4412板级文件

cp board/samsung/origen/  board/samsung/tiny4412/

cd board/samsung/tiny4412/tools/

mv mkorigenspl.c mktiny4412spl.c

cd board/samsung/tiny4412/

mv origen.c  tiny4412.c

2.3.1. 修改文件board/samsung/tiny4412/Makefile，如下：

@@ -6,7 +6,7 @@
 # necessary to create built-in.o
 obj- := __dummy__.o
 
-hostprogs-y := tools/mkorigenspl
+hostprogs-y := tools/mktiny4412spl
 always := $(hostprogs-y)
 
 # omit -O2 option to suppress
@@ -14,7 +14,7 @@
 #
 # TODO:
 # Fix the root cause in tools/mkorigenspl.c and delete the following work-around
-$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
+$(obj)/tools/mktiny4412spl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
 else
-obj-y	+= origen.o
+obj-y	+= tiny4412.o
 endif

2.3.2. 修改文件board/samsung/tiny4412/Kconfig，如下：


@@ -1,12 +1,12 @@
-if TARGET_ORIGEN
+if TARGET_TINY4412
 
 config SYS_BOARD
-	default "origen"
+	default "tiny4412"
 
 config SYS_VENDOR
 	default "samsung"
 
 config SYS_CONFIG_NAME
-	default "origen"
+	default "tiny4412"
 
 endif

2.3.3. 修改文件board/samsung/tiny4412/MAINTAINERS，如下：

@@ -1,6 +1,6 @@
-ORIGEN BOARD
-M:	Chander Kashyap <k.chander@samsung.com>
+TINY4412 BOARD
+M:	Liu guichao <gccb@foxmail.com>
 S:	Maintained
-F:	board/samsung/origen/
-F:	include/configs/origen.h
-F:	configs/origen_defconfig
+F:	board/samsung/tiny4412/
+F:	include/configs/tiny4412.h
+F:	configs/tiny4412_defconfig

---------------------------------------------------------

2.4. 复制tiny4412头文件

cp include/configs/origen.h include/configs/tiny4412.h

修改文件include/configs/tiny4412.h，如下：

@@ -2,19 +2,19 @@
 /*
  * Copyright (C) 2011 Samsung Electronics
  *
- * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.
+ * Configuration settings for the SAMSUNG TINY4412 (EXYNOS4412) board.
  */
 
-#ifndef __CONFIG_ORIGEN_H
-#define __CONFIG_ORIGEN_H
+#ifndef __CONFIG_TINY4412_H
+#define __CONFIG_TINY4412_H
 
 #include <configs/exynos4-common.h>
 
 /* High Level Configuration Options */
-#define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
-#define CONFIG_ORIGEN			1	/* working with ORIGEN*/
+#define CONFIG_EXYNOS4412		1	/* which is a EXYNOS4412 SoC */
+#define CONFIG_TINY4412			1	/* working with TINY4412*/
 
-/* ORIGEN has 4 bank of DRAM */
+/* TINY4412 has 4 bank of DRAM */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
 #define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
@@ -22,12 +22,12 @@
 /* memtest works on */
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
 
-#define CONFIG_MACH_TYPE		MACH_TYPE_ORIGEN
+#define CONFIG_MACH_TYPE		MACH_TYPE_TINY4412
 
 /* select serial console configuration */
 
 /* Console configuration */
-#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC0,115200n8\0"
 
 #define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
 
@@ -46,7 +46,7 @@
 	"rdaddr=0x48000000\0" \
 	"kerneladdr=0x40007000\0" \
 	"ramdiskaddr=0x48000000\0" \
-	"console=ttySAC2,115200n8\0" \
+	"console=ttySAC0,115200n8\0" \
 	"mmcdev=0\0" \
 	"bootenv=uEnv.txt\0" \
 	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
@@ -78,15 +78,25 @@
 #define CONFIG_MIU_2BIT_21_7_INTERLEAVED
 
 #define RESERVE_BLOCK_SIZE		(512)
-#define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
+#define BL1_SIZE			(8 << 10) /*8 K reserved for BL1*/
+#define BL2_SIZE			(16 << 10) /*16 K reserved for BL2*/
 
 #define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
 
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_INIT_SP_ADDR		0x02040000
+#else
+//#define CONFIG_SYS_INIT_SP_ADDR		((CONFIG_SYS_LOAD_ADDR) - 0x1000000)
+#define CONFIG_SYS_INIT_SP_ADDR		0x42E00000
+#endif
 
 /* U-Boot copy size from boot Media to DRAM.*/
-#define COPY_BL2_SIZE		0x80000
-#define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
-#define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)
+#define COPY_UBOOT_SIZE		0xC8000 //800KB
+#define UBOOT_START_OFFSET	((RESERVE_BLOCK_SIZE + BL1_SIZE + BL2_SIZE) /512)
+#define UBOOT_SIZE_BLOC_COUNT	(COPY_UBOOT_SIZE /512)
+
+#define COPY_BL2_SIZE		0x4000
+#define BL2_START_OFFSET	((RESERVE_BLOCK_SIZE + BL1_SIZE) /512)
+#define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE /512)
 
-#endif	/* __CONFIG_H */
+#endif	/* __CONFIG_TINY4412_H */

2.5. 复制文件tiny4412默认配置文件

configs/origen_defconfig configs/tiny4412_defconfig

修改如下：

@@ -4,19 +4,25 @@
 CONFIG_ARCH_EXYNOS=y
 CONFIG_SYS_TEXT_BASE=0x43E00000
 CONFIG_ARCH_EXYNOS4=y
-CONFIG_TARGET_ORIGEN=y
+CONFIG_TARGET_TINY4412=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x13800000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x4200
-CONFIG_SPL_TEXT_BASE=0x02021410
+CONFIG_SPL_TEXT_BASE=0x02023400
 CONFIG_SPL=y
-CONFIG_IDENT_STRING=" for ORIGEN"
-CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_IDENT_STRING=" for TINY4412"
+CONFIG_DEFAULT_DEVICE_TREE="exynos4412-tiny4412"
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SYS_PROMPT="ORIGEN # "
+CONFIG_SYS_PROMPT="TINY4412 # "
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y

2.6. 修改文件scripts/config_whitelist.txt

增加CONFIG_EXYNOS4412， CONFIG_TINY4412，注意按字母顺序添加如下：

@@ -470,6 +470,7 @@
 CONFIG_EXT_USB_HOST_BASE
 CONFIG_EXYNOS4
 CONFIG_EXYNOS4210
+CONFIG_EXYNOS4412
 CONFIG_EXYNOS5
 CONFIG_EXYNOS5250
 CONFIG_EXYNOS5420
@@ -3914,6 +3915,7 @@
 CONFIG_THOR_RESET_OFF
 CONFIG_THUNDERX
 CONFIG_TIMESTAMP
+CONFIG_TINY4412
 CONFIG_TIZEN
 CONFIG_TI_KSNAV
 CONFIG_TMU_TIMER

-------------------------------------------------------

做完以上的工作之后，其实可以退出make menuconfig,然后执行make tiny4412_defconfig, 这样就把上面的配置加载到.config，供编译的时候使用。

前面之所以开始运行make menuconfig,是为了寻找一个合适的配置供我们参考。最终把配置写到了tiny4412_defconfig。

三、设备树文件修改

tiny4412_defconfig中关于设备树的配置如下：

ONFIG_DEFAULT_DEVICE_TREE="exynos4412-tiny4412"

所以在arch/arm/dts/目录下，增加exynos4412-tiny4412.dts文件，同样，

先复制文件 cp arch/arm/dts/exynos4210-origen.dts arch/arm/dts/exynos4412-tiny4412.dts

修改exynos4412-tiny4412.dts文件，如下：

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Samsung's Exynos4210 based Origen board device tree source
+ * Samsung's Exynos4412 based Tiny4412 board device tree source
  *
  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
@@ -8,11 +8,11 @@
 
 /dts-v1/;
 #include "skeleton.dtsi"
-#include "exynos4210.dtsi"
+#include "exynos4412.dtsi"
 
 / {
-	model = "Insignal Origen evaluation board based on Exynos4210";
-	compatible = "insignal,origen", "samsung,exynos4210";
+	model = "Tiny4412(v1412) board based on Exynos4412 \r\nModified by Liu Guichao<gccb@foxmail.com>";
+	compatible = "insignal,tiny4412", "samsung,exynos4412";
 
 	chosen {
 		bootargs ="";
@@ -20,7 +20,7 @@
 
 	aliases {
 		serial0 = "/serial@13800000";
-		console = "/serial@13820000";
+		console = "/serial@13800000";
 	};
 };

修改文件arch/arm/dts/Makefile，增加exynos4412-tiny4412.dtb \如下：

@@ -12,6 +12,7 @@
 	exynos4210-universal_c210.dtb \
 	exynos4210-trats.dtb \
 	exynos4412-trats2.dtb \
+	exynos4412-tiny4412.dtb \
 	exynos4412-odroid.dtb
 
 dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb

四、Soc级别的修改

路径 arch/arm/mach-exynos/ 中都是关于exynos系列芯片的代码，时钟的修改，DRAM的开启等都在这里。不过这里提供的仅为通用的代码。对于特定的exynos4412芯片，并未特别指出。所以我在这个目录下复制添加如下文件：

cd arch/arm/mach-exynos/

cp clock_init_exynos4.c clock_init_exynos4412.c

cp dmc_init_exynos4.c dmc_init_exynos4412.c

cp exynos4_setup.h exynos4412_setup.h

--------------------------------------------------------------

4.0.修改文件arch/arm/mach-exynos/include/mach/clock.h

@@ -513,6 +513,287 @@
 	unsigned int	cmu_isp_spar3;
 };
 
+struct exynos4412_clock {
+	unsigned char	res1[0x4200];
+	unsigned int	src_leftbus;
+	unsigned char	res2[0x1fc];
+	unsigned int	mux_stat_leftbus;
+	unsigned char	res3[0xfc];
+	unsigned int	div_leftbus;
+	unsigned char	res4[0xfc];
+	unsigned int	div_stat_leftbus;
+	unsigned char	res5[0x1fc];
+	unsigned int	gate_ip_leftbus;
+	unsigned char	res6[0x12c];
+	unsigned int	gate_ip_image;
+	unsigned char	res7[0xcc];
+	unsigned int	clkout_cmu_leftbus;
+	unsigned int	clkout_cmu_leftbus_div_stat;
+	unsigned char	res8[0x37f8];
+	unsigned int	src_rightbus;
+	unsigned char	res9[0x1fc];
+	unsigned int	mux_stat_rightbus;
+	unsigned char	res10[0xfc];
+	unsigned int	div_rightbus;
+	unsigned char	res11[0xfc];
+	unsigned int	div_stat_rightbus;
+	unsigned char	res12[0x1fc];
+	unsigned int	gate_ip_rightbus;
+	unsigned char	res13[0x15c];
+	unsigned int	gate_ip_perir;
+	unsigned char	res14[0x9c];
+	unsigned int	clkout_cmu_rightbus;
+	unsigned int	clkout_cmu_rightbus_div_stat;
+	unsigned char	res15[0x3608];
+	unsigned int	epll_lock;
+	unsigned char	res16[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res17[0xec];
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned int	epll_con2;
+	unsigned char	res18[0x4];
+	unsigned int	vpll_con0;
+	unsigned int	vpll_con1;
+	unsigned int	vpll_con2;
+	unsigned char	res19[0xe4];
+	unsigned int	src_top0;
+	unsigned int	src_top1;
+	unsigned char	res20[0x8];
+	unsigned int	src_cam0;
+	unsigned int	src_tv;
+	unsigned int	src_mfc;
+	unsigned int	src_g3d;
+	unsigned char	res21[0x4];
+	unsigned int	src_lcd;
+	unsigned int	src_isp;
+	unsigned int	src_maudio;
+	unsigned int	src_fsys;
+	unsigned char	res22[0xc];
+	unsigned int	src_peril0;
+	unsigned int	src_peril1;
+	unsigned int	src_cam1;
+	unsigned char	res23[0xb4];
+	unsigned int	src_mask_top;//4412 is reserved
+	unsigned char	res24[0xc];
+	unsigned int	src_mask_cam0;
+	unsigned int	src_mask_tv;
+	unsigned char	res25[0xc];
+	unsigned int	src_mask_lcd;
+	unsigned int	src_mask_isp;
+	unsigned int	src_mask_maudio;
+	unsigned int	src_mask_fsys;
+	unsigned char	res26[0xc];
+	unsigned int	src_mask_peril0;
+	unsigned int	src_mask_peril1;
+	unsigned char	res27[0xb8];
+	unsigned int	mux_stat_top0;
+	unsigned int	mux_stat_top1;
+	unsigned char	res28[0x10];
+	unsigned int	mux_stat_mfc;
+	unsigned int	mux_stat_g3d;
+	unsigned char	res29[0x28];
+	unsigned int	mux_stat_cam1;
+	unsigned char	res30[0xb4];
+	unsigned int	div_top;
+	unsigned char	res31[0xc];
+	unsigned int	div_cam0;
+	unsigned int	div_tv;
+	unsigned int	div_mfc;
+	unsigned int	div_g3d;
+	unsigned char	res32[0x4];
+	unsigned int	div_lcd;
+	unsigned int	div_isp;
+	unsigned int	div_maudio;
+	unsigned int	div_fsys0;
+	unsigned int	div_fsys1;
+	unsigned int	div_fsys2;
+	unsigned int	div_fsys3;
+	unsigned int	div_peril0;
+	unsigned int	div_peril1;
+	unsigned int	div_peril2;
+	unsigned int	div_peril3;
+	unsigned int	div_peril4;
+	unsigned int	div_peril5;
+	unsigned int	div_cam1;
+	unsigned char	res33[0x14];
+	unsigned int	div2_ratio;
+	unsigned char	res34[0x8c];
+	unsigned int	div_stat_top;
+	unsigned char	res35[0xc];
+	unsigned int	div_stat_cam0;
+	unsigned int	div_stat_tv;
+	unsigned int	div_stat_mfc;
+	unsigned int	div_stat_g3d;
+	unsigned char	res36[0x4];
+	unsigned int	div_stat_lcd;
+	unsigned int	div_stat_isp;
+	unsigned int	div_stat_maudio;
+	unsigned int	div_stat_fsys0;
+	unsigned int	div_stat_fsys1;
+	unsigned int	div_stat_fsys2;
+	unsigned int	div_stat_fsys3;
+	unsigned int	div_stat_peril0;
+	unsigned int	div_stat_peril1;
+	unsigned int	div_stat_peril2;
+	unsigned int	div_stat_peril3;
+	unsigned int	div_stat_peril4;
+	unsigned int	div_stat_peril5;
+	unsigned int	div_stat_cam1;
+	unsigned char	res37[0x14];
+	unsigned int	div2_stat;
+	//unsigned char	res38[0x29c];
+	unsigned char	res38[0xc0];//4412 add
+	unsigned int	gate_bus_fsys1;//4412 add
+	unsigned char	res38_1[0x1d8];//4412 add
+	unsigned int	gate_ip_cam;
+	unsigned int	gate_ip_tv;
+	unsigned int	gate_ip_mfc;
+	unsigned int	gate_ip_g3d;
+	unsigned char	res39[0x4];
+	unsigned int	gate_ip_lcd;
+	unsigned int	gate_ip_isp;
+	unsigned int	gate_ip_fsys;
+	unsigned char	res40[0x4];
+	unsigned char	res41[0x8];
+	unsigned int	gate_ip_gps;
+	unsigned int	gate_ip_peril;
+	unsigned char	res42[0x1c];
+	//unsigned char	res43[0x4];
+	//unsigned char	res44[0xc];
+	unsigned int	gate_block;
+	unsigned char	res45[0x8c];
+	unsigned int	clkout_cmu_top;
+	unsigned int	clkout_cmu_top_div_stat;
+	unsigned char	res46[0x3600];
+	unsigned int	mpll_lock;
+	unsigned char	res47[0xfc];
+	unsigned int	mpll_con0;
+	unsigned int	mpll_con1;
+	unsigned char	res48[0xf0];
+	unsigned int	src_dmc;
+	unsigned char	res49[0xfc];
+	unsigned int	src_mask_dmc;
+	unsigned char	res50[0xfc];
+	unsigned int	mux_stat_dmc;
+	unsigned char	res51[0xfc];
+	unsigned int	div_dmc0;
+	unsigned int	div_dmc1;
+	unsigned char	res52[0xf8];
+	unsigned int	div_stat_dmc0;
+	unsigned int	div_stat_dmc1;
+	unsigned char	res53[0xf8];
+	unsigned int	gate_bus_dmc0;
+	unsigned int	gate_bus_dmc1;
+	unsigned char	res54[0x1f8];
+	unsigned int	gate_ip_dmc0;
+	unsigned int	gate_ip_dmc1;
+	unsigned char	res55[0xf8];
+	unsigned int	clkout_cmu_dmc;
+	unsigned int	clkout_cmu_dmc_div_stat;
+	unsigned char	res56[0x5f8];
+	unsigned int	dcgidx_map0;
+	unsigned int	dcgidx_map1;
+	unsigned int	dcgidx_map2;
+	unsigned char	res57[0x14];
+	unsigned int	dcgperf_map0;
+	unsigned int	dcgperf_map1;
+	unsigned char	res58[0x18];
+	unsigned int	dvcidx_map;
+	unsigned char	res59[0x1c];
+	unsigned int	freq_cpu;
+	unsigned int	freq_dpm;
+	unsigned char	res60[0x18];
+	unsigned int	dvsemclk_en;
+	unsigned int	maxperf;
+	unsigned char	res61[0xc];
+	//unsigned int	dmc_freq_ctrl;
+	unsigned int	dmc_pause_ctrl;
+	unsigned int	dddrphy_lock_ctrl;
+	unsigned int	c2c_state;
+	unsigned char	res62[0x2f60];
+	unsigned int	apll_lock;
+	unsigned char	res63[0x8];
+	unsigned char	res64[0xf4];
+	unsigned int	apll_con0;
+	unsigned int	apll_con1;
+	unsigned char	res65[0xf8];
+	unsigned int	src_cpu;
+	unsigned char	res66[0x1fc];
+	unsigned int	mux_stat_cpu;
+	unsigned char	res67[0xfc];
+	unsigned int	div_cpu0;
+	unsigned int	div_cpu1;
+	unsigned char	res68[0xf8];
+	unsigned int	div_stat_cpu0;
+	unsigned int	div_stat_cpu1;
+	unsigned char	res69[0x2f8];
+	unsigned int	clk_gate_ip_cpu;
+	unsigned char	res70[0xfc];
+	unsigned int	clkout_cmu_cpu;
+	unsigned int	clkout_cmu_cpu_div_stat;
+	unsigned char	res71[0x5f8];
+	unsigned int	armclk_stopctrl;
+	unsigned int	atclk_stopctrl;
+	unsigned char	res72[0x10];
+	unsigned char	res73[0x8];
+	unsigned int	pwr_ctrl;
+	unsigned int	pwr_ctrl2;
+	unsigned char	res74[0x3d8];
+	/*
+	unsigned int	apll_con0_l8;
+	unsigned int	apll_con0_l7;
+	unsigned int	apll_con0_l6;
+	unsigned int	apll_con0_l5;
+	unsigned int	apll_con0_l4;
+	unsigned int	apll_con0_l3;
+	unsigned int	apll_con0_l2;
+	unsigned int	apll_con0_l1;
+	unsigned int	iem_control;
+	unsigned char	res75[0xdc];
+	unsigned int	apll_con1_l8;
+	unsigned int	apll_con1_l7;
+	unsigned int	apll_con1_l6;
+	unsigned int	apll_con1_l5;
+	unsigned int	apll_con1_l4;
+	unsigned int	apll_con1_l3;
+	unsigned int	apll_con1_l2;
+	unsigned int	apll_con1_l1;
+	unsigned char	res76[0xe0];
+	unsigned int	div_iem_l8;
+	unsigned int	div_iem_l7;
+	unsigned int	div_iem_l6;
+	unsigned int	div_iem_l5;
+	unsigned int	div_iem_l4;
+	unsigned int	div_iem_l3;
+	unsigned int	div_iem_l2;
+	unsigned int	div_iem_l1;
+	unsigned char	res77[0xe0];
+	*/
+	unsigned int	l2_status;
+	unsigned char	res78[0xc];
+	unsigned int	cpu_status;
+	unsigned char	res79[0xc];
+	unsigned int	ptm_status;
+	unsigned char	res80[0x2edc];
+	unsigned int	div_isp0;
+	unsigned int	div_isp1;
+	unsigned char	res81[0xf8];
+	unsigned int	div_stat_isp0;
+	unsigned int	div_stat_isp1;
+	unsigned char	res82[0x3f8];
+	unsigned int	gate_ip_isp0;
+	unsigned int	gate_ip_isp1;
+	unsigned char	res83[0x1f8];
+	unsigned int	clkout_cmu_isp;
+	unsigned int	clkout_cmu_isp_div_stat;
+	unsigned char	res84[0xf8];
+	unsigned int	cmu_isp_spar0;
+	unsigned int	cmu_isp_spar1;
+	unsigned int	cmu_isp_spar2;
+	unsigned int	cmu_isp_spar3;
+};
+
 struct exynos5_clock {
 	unsigned int	apll_lock;
 	unsigned char	res1[0xfc];

4.1. 修改文件arch/arm/mach-exynos/clock_init_exynos4412.c

这个文件是关于exynos4412芯片时钟的配置，如下：

@@ -30,7 +30,7 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/clock.h>
 #include "common_setup.h"
-#include "exynos4_setup.h"
+#include "exynos4412_setup.h"
 
 /*
  * system_clock_init: Initialize core clock and bus clock.
@@ -38,24 +38,23 @@
  */
 void system_clock_init(void)
 {
-	struct exynos4_clock *clk =
-			(struct exynos4_clock *)samsung_get_base_clock();
+	struct exynos4412_clock *clk =
+			(struct exynos4412_clock *)samsung_get_base_clock();
 
-	writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+	writel(CLK_SRC_CPU_VAL_FINPLL, &clk->src_cpu);
 
 	sdelay(0x10000);
-
-	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_DMC_VAL_FINPLL, &clk->src_dmc);
+	writel(CLK_SRC_TOP0_VAL_RESET, &clk->src_top0);
 	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
-	writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
 	writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
 	writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
 	writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
 	writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
-	writel(CLK_SRC_CAM_VAL, &clk->src_cam);
+	writel(CLK_SRC_CAM_VAL, &clk->src_cam0);
 	writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
 	writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
-	writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
+	writel(CLK_SRC_LCD0_VAL, &clk->src_lcd);
 
 	sdelay(0x10000);
 
@@ -70,10 +69,10 @@
 	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
 	writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
 	writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
-	writel(CLK_DIV_CAM_VAL, &clk->div_cam);
+	writel(CLK_DIV_CAM_VAL, &clk->div_cam0);
 	writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
 	writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
-	writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
+	writel(CLK_DIV_LCD0_VAL, &clk->div_lcd);
 
 	/* Set PLL locktime */
 	writel(PLL_LOCKTIME, &clk->apll_lock);
@@ -91,4 +90,9 @@
 	writel(VPLL_CON0_VAL, &clk->vpll_con0);
 
 	sdelay(0x30000);
+	
+	writel(CLK_SRC_CPU_VAL_APLL, &clk->src_cpu);
+	writel(CLK_SRC_DMC_VAL_MPLL, &clk->src_dmc);
+	writel(CLK_SRC_TOP0_VAL_UP_V_E_PLL, &clk->src_top0);
+	
 }

4.2. 修改文件arch/arm/mach-exynos/dmc_init_exynos4412.c，如下：

@@ -4,6 +4,8 @@
  * Copyright (C) 2013 Samsung Electronics
  * Rajeshwari Shinde <rajeshwari.s@samsung.com>
  *
+ *LiuGuiChao <gccb@foxmail.com> Modify.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -25,8 +27,9 @@
 
 #include <config.h>
 #include <asm/arch/dmc.h>
+#include <debug_uart.h>
 #include "common_setup.h"
-#include "exynos4_setup.h"
+#include "exynos4412_setup.h"
 
 struct mem_timings mem = {
 	.direct_cmd_msr = {
@@ -45,9 +48,50 @@
 	.memcontrol = MEMCONTROL_VAL,
 	.memconfig0 = MEMCONFIG0_VAL,
 	.memconfig1 = MEMCONFIG1_VAL,
+	.ivcontrol = IVCONTROL_VAL,
 	.dll_resync = FORCE_DLL_RESYNC,
 	.dll_on = DLL_CONTROL_ON,
 };
+
+#ifdef CONFIG_TINY4412
+/*简易测试tiny4412内存情况,如果读出的值正常，即初步判断内存初始化正常*/
+void tiny4412_mem_test(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	unsigned int i;
+
+	printascii("Simple Memory test start...\r\n");
+	printascii("write 0x12345678 ...\r\n");
+	for (i = 0x40000000;
+		i < 0x80000000; i+=0x10000000)
+	{
+		writel(0x12345678, i);
+		printascii("addr:0x");
+		printhex8(i);
+		printascii("--data:");
+		printascii("0x");
+		printhex8(readl(i));
+		printascii("\r\n");
+	}
+	printascii("write 0x89abcdef ...\r\n");
+	for (i = 0x4FFFFFFC;
+		i <= 0x7FFFFFFC; i+=0x10000000)
+	{
+		writel(0x89ABCDEF, i);
+		printascii("addr:0x");
+		printhex8(i);
+		printascii("--data:");
+		printascii("0x");
+		printhex8(readl(i));
+		printascii("\r\n");
+	}
+	printascii("Memory test end.\r\n\r\n");
+#endif		
+	
+}
+#endif
+
+
 static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
 {
 	if (ctrl_no) {
@@ -55,6 +99,9 @@
 		       &dmc->phycontrol1);
 		writel((mem.control1 | (0 << mem.dll_resync)),
 		       &dmc->phycontrol1);
+
+		/*datasheet P1060 18.9 Memory Channels Interleavings*/
+		writel(mem.ivcontrol, &dmc->ivcontrol);
 	} else {
 		writel((mem.control0 | (0 << mem.dll_on)),
 		       &dmc->phycontrol0);
@@ -79,6 +126,7 @@
 
 static void dmc_init(struct exynos4_dmc *dmc)
 {
+
 	/*
 	 * DLL Parameter Setting:
 	 * Termination: Enable R/W
@@ -114,7 +162,7 @@
 
 	/*
 	 * Memor Burst length: 8
-	 * Number of chips: 2
+	 * Number of chips: 1
 	 * Memory Bus width: 32 bit
 	 * Memory Type: DDR3
 	 * Additional Latancy for PLL: 1 Cycle
@@ -175,7 +223,7 @@
 	 * 0: full_sync
 	 */
 	writel(1, ASYNC_CONFIG);
-#ifdef CONFIG_ORIGEN
+#if defined(CONFIG_ORIGEN) || defined(CONFIG_TINY4412)
 	/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
 	writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
 		APB_SFR_INTERLEAVE_CONF_OFFSET);
@@ -210,4 +258,9 @@
 	dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl()
 					+ DMC_OFFSET);
 	dmc_init(dmc);
+
+#ifdef CONFIG_TINY4412
+	tiny4412_mem_test();
+#endif
+
 }

4.3. 修改文件arch/arm/mach-exynos/exynos4412_setup.h，如下：

@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Machine Specific Values for EXYNOS4012 based board
+ * Machine Specific Values for EXYNOS4412 based board
  *
  * Copyright (C) 2011 Samsung Electronics
  */
 
-#ifndef _ORIGEN_SETUP_H
-#define _ORIGEN_SETUP_H
+#ifndef _EXYNOS4412_SETUP_H
+#define _EXYNOS4412_SETUP_H
 
 #include <config.h>
 #include <asm/arch/cpu.h>
@@ -28,150 +28,333 @@
 #define ASYNC_CONFIG		0x10010350
 
 /* CLK_SRC_CPU */
-#define MUX_HPM_SEL_MOUTAPLL		0x0
-#define MUX_HPM_SEL_SCLKMPLL		0x1
-#define MUX_CORE_SEL_MOUTAPLL		0x0
-#define MUX_CORE_SEL_SCLKMPLL		0x1
-#define MUX_MPLL_SEL_FILPLL		0x0
-#define MUX_MPLL_SEL_MOUTMPLLFOUT	0x1
-#define MUX_APLL_SEL_FILPLL		0x0
-#define MUX_APLL_SEL_MOUTMPLLFOUT	0x1
-#define CLK_SRC_CPU_VAL			((MUX_HPM_SEL_MOUTAPLL << 20) \
-					| (MUX_CORE_SEL_MOUTAPLL << 16) \
-					| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
-					| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
+#define MUX_MPLL_USER_SEL_C_SEL_FILPLL			0x0
+#define MUX_MPLL_USER_SEL_C_SEL_FOUTMPLL		0x1
+#define MUX_HPM_SEL_MOUTAPLL				0x0
+#define MUX_HPM_SEL_SCLKMPLL				0x1
+#define MUX_CORE_SEL_MOUTAPLL				0x0
+#define MUX_CORE_SEL_SCLKMPLL				0x1
+#define MUX_APLL_SEL_FILPLL				0x0
+#define MUX_APLL_SEL_MOUTAPLLFOUT			0x1
+
+#define MUX_MPLL_USER_SEL_C_SEL_OFFSET			24
+#define MUX_HPM_SEL_OFFSET				20
+#define MUX_CORE_SEL_OFFSET				16
+#define MUX_APLL_SEL_OFFSET				0
+
+/*使用外部时钟*/
+#define CLK_SRC_CPU_VAL_FINPLL \
+	((MUX_MPLL_USER_SEL_C_SEL_FOUTMPLL << MUX_MPLL_USER_SEL_C_SEL_OFFSET) \
+	| (MUX_HPM_SEL_MOUTAPLL << MUX_HPM_SEL_OFFSET) \
+	| (MUX_CORE_SEL_MOUTAPLL << MUX_CORE_SEL_OFFSET)\
+	| (MUX_APLL_SEL_FILPLL << MUX_APLL_SEL_OFFSET))
+
+/*使用APLL时钟*/
+#define CLK_SRC_CPU_VAL_APLL \
+	(MUX_APLL_SEL_MOUTAPLLFOUT << MUX_APLL_SEL_OFFSET)
+
+/*
+CMU_CPU
+freq(SCLK_APLL) 	= 1400MHz   P=3 M=175 S=0   //APLL锁相环
+freq(ARMCLK)        	= 1400MHz
+freq(ACLK_COREM0)	= 350MHz
+freq(ACLK_CORES)	= 1400MHz
+freq(ACLK_COREM1)	= 175MHz
+freq(PERIPHCLK)		= 1400MHz
+freq(ATCLK)		= 200MHz  //P898
+freq(PCLK_DBG)		= 100MHz
+freq(SCLK_HPM)		= 350MHz
+freq(SCLKMPLL_USER_C)	= freq(SCLK_APLL) 
+*/
 
 /* CLK_DIV_CPU0 */
-#define APLL_RATIO		0x0
-#define PCLK_DBG_RATIO		0x1
-#define ATB_RATIO		0x3
-#define PERIPH_RATIO		0x3
-#define COREM1_RATIO		0x7
-#define COREM0_RATIO		0x3
-#define CORE_RATIO		0x0
-#define CLK_DIV_CPU0_VAL	((APLL_RATIO << 24) \
-				| (PCLK_DBG_RATIO << 20) \
-				| (ATB_RATIO << 16) \
-				| (PERIPH_RATIO << 12) \
-				| (COREM1_RATIO << 8) \
-				| (COREM0_RATIO << 4) \
-				| (CORE_RATIO << 0))
+#define APLL_RATIO		0x0	//1400MHz
+#define CORE_RATIO		0x0	//1400MHz
+#define CORE2_RATIO		0x0	//1400MHz
+#define COREM0_RATIO		0x3	//350MHz
+#define COREM1_RATIO		0x7	//175MHz
+#define PERIPH_RATIO		0x0	//1400MHz
+#define ATB_RATIO		0x6	//200MHz
+#define PCLK_DBG_RATIO		0x1	//100MHz	
+
+#define CORE2_RATIO_OFFSET		28				
+#define APLL_RATIO_OFFSET		24
+#define PCLK_DBG_RATIO_OFFSET		20
+#define ATB_RATIO_OFFSET		16
+#define PERIPH_RATIO_OFFSET		12
+#define COREM1_RATIO_OFFSET		8
+#define COREM0_RATIO_OFFSET		4
+#define CORE_RATIO_OFFSET		0
+
+#define CLK_DIV_CPU0_VAL \
+	((CORE2_RATIO << CORE2_RATIO_OFFSET) \
+	| (APLL_RATIO << APLL_RATIO_OFFSET) \
+	| (PCLK_DBG_RATIO << PCLK_DBG_RATIO_OFFSET) \
+	| (ATB_RATIO << ATB_RATIO_OFFSET) \
+	| (PERIPH_RATIO << PERIPH_RATIO_OFFSET) \
+	| (COREM1_RATIO << COREM1_RATIO_OFFSET) \
+	| (COREM0_RATIO << COREM0_RATIO_OFFSET) \
+	| (CORE_RATIO << CORE_RATIO_OFFSET))
 
 /* CLK_DIV_CPU1 */
-#define HPM_RATIO		0x0
-#define COPY_RATIO		0x3
-#define CLK_DIV_CPU1_VAL	((HPM_RATIO << 4) | (COPY_RATIO))
+#define COPY_RATIO			0x3
+#define HPM_RATIO			0x0
+#define CORES_RATIO			0x0
+
+#define CORES_RATIO_OFFSET		8
+#define HPM_RATIO_OFFSET		4
+#define COPY_RATIO_OFFSET		0
+
+#define CLK_DIV_CPU1_VAL \
+	((CORES_RATIO << CORES_RATIO_OFFSET) \
+	| (HPM_RATIO << HPM_RATIO_OFFSET) \
+	| (COPY_RATIO << COPY_RATIO_OFFSET))
 
+/****************************************************************/
 /* CLK_SRC_DMC */
-#define MUX_PWI_SEL_XXTI		0x0
-#define MUX_PWI_SEL_XUSBXTI		0x1
-#define MUX_PWI_SEL_SCLK_HDMI24M	0x2
-#define MUX_PWI_SEL_SCLK_USBPHY0	0x3
-#define MUX_PWI_SEL_SCLK_USBPHY1	0x4
-#define MUX_PWI_SEL_SCLK_HDMIPHY	0x5
-#define MUX_PWI_SEL_SCLKMPLL		0x6
-#define MUX_PWI_SEL_SCLKEPLL		0x7
-#define MUX_PWI_SEL_SCLKVPLL		0x8
-#define MUX_DPHY_SEL_SCLKMPLL		0x0
-#define MUX_DPHY_SEL_SCLKAPLL		0x1
-#define MUX_DMC_BUS_SEL_SCLKMPLL	0x0
-#define MUX_DMC_BUS_SEL_SCLKAPLL	0x1
-#define CLK_SRC_DMC_VAL			((MUX_PWI_SEL_XUSBXTI << 16) \
-					| (MUX_DPHY_SEL_SCLKMPLL << 8) \
-					| (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
+#define MUX_G2D_ACP_SEL_MOUTG2D_ACP_0		0x0
+#define MUX_G2D_ACP_SEL_MOUTG2D_ACP_1		0x1
+#define MUX_G2D_ACP_1_SEL_SCLKEPLL		0x0
+#define MUX_G2D_ACP_1_SEL_SCLKVPLL		0x1
+#define MUX_G2D_ACP_0_SEL_SCLKEPLL		0x0
+#define MUX_G2D_ACP_0_SEL_SCLKVPLL		0x1
+#define MUX_PWI_SEL_XXTI			0x0
+#define MUX_PWI_SEL_XUSBXTI			0x1
+#define MUX_PWI_SEL_SCLK_HDMI24M		0x2
+#define MUX_PWI_SEL_SCLK_USBPHY0		0x3
+#define MUX_PWI_SEL_SCLK_USBPHY1		0x4
+#define MUX_PWI_SEL_SCLK_HDMIPHY		0x5
+#define MUX_PWI_SEL_SCLKMPLL			0x6
+#define MUX_PWI_SEL_SCLKEPLL			0x7
+#define MUX_PWI_SEL_SCLKVPLL			0x8
+#define MUX_MPLL_SEL_FINPLL			0x0
+#define MUX_MPLL_SEL_MOUTMPLLFOUT		0x1
+#define MUX_DPHY_SEL_SCLKMPLL			0x0
+#define MUX_DPHY_SEL_SCLKAPLL			0x1
+#define MUX_DMC_BUS_SEL_SCLKMPLL		0x0
+#define MUX_DMC_BUS_SEL_SCLKAPLL		0x1
+#define MUX_C2C_SEL_SCLKMPLL			0x0
+#define MUX_C2C_SEL_SCLKAPLL			0x1
+
+#define MUX_G2D_ACP_SEL_OFFSET			28
+#define MUX_G2D_ACP_1_SEL_OFFSET		24
+#define MUX_G2D_ACP_0_SEL_OFFSET		20
+#define MUX_PWI_SEL_OFFSET			16
+#define MUX_MPLL_SEL_OFFSET			12
+#define MUX_DPHY_SEL_OFFSET			8
+#define MUX_DMC_BUS_SEL_OFFSET			4
+#define MUX_C2C_SEL_OFFSET			0
+
+
+#define CLK_SRC_DMC_VAL_FINPLL			\
+	((MUX_MPLL_SEL_FINPLL << MUX_MPLL_SEL_OFFSET) \
+	| (MUX_C2C_SEL_SCLKMPLL << MUX_C2C_SEL_OFFSET) \
+	| (MUX_DMC_BUS_SEL_SCLKMPLL << MUX_DMC_BUS_SEL_OFFSET) \
+	| (MUX_DPHY_SEL_SCLKMPLL << MUX_DPHY_SEL_OFFSET) \
+	| (MUX_PWI_SEL_SCLKMPLL << MUX_PWI_SEL_OFFSET))
+
+#define CLK_SRC_DMC_VAL_MPLL			\
+	(MUX_MPLL_SEL_MOUTMPLLFOUT << MUX_MPLL_SEL_OFFSET) 
+
+/* CMU_DMC
+freq(SCLK_MPLL) 	= 800MHz    P=3 M=100 S=0
+freq(ACLK_C2C) 		= 200MHz
+freq(SCLK_C2C) 		= 400MHz
+freq(SCLK_DMC)		= 400MHz    P441
+freq(ACLK_DMCD) 	= 200MHz
+freq(ACLK_DMCP) 	= 100MHz
+freq(ACLK_ACP) 		= 200MHz
+freq(PCLK_ACP) 		= 100MHz
+freq(SCLK_DPHY)		= 400MHz
+freq(IECDPMCLKEN)	= default
+freq(IECDVSEMCLKEN)	= default
+freq(SCLK_PWI)		= default
+freq(SCLK_G2D_ACP)	= default
+*/
 
 /* CLK_DIV_DMC0 */
-#define CORE_TIMERS_RATIO	0x1
-#define COPY2_RATIO		0x3
-#define DMCP_RATIO		0x1
+#define DMCP_RATIO		0x1	
 #define DMCD_RATIO		0x1
 #define DMC_RATIO		0x1
 #define DPHY_RATIO		0x1
 #define ACP_PCLK_RATIO		0x1
 #define ACP_RATIO		0x3
-#define CLK_DIV_DMC0_VAL	((CORE_TIMERS_RATIO << 28) \
-				| (COPY2_RATIO << 24) \
-				| (DMCP_RATIO << 20) \
-				| (DMCD_RATIO << 16) \
-				| (DMC_RATIO << 12) \
-				| (DPHY_RATIO << 8) \
-				| (ACP_PCLK_RATIO << 4)	\
-				| (ACP_RATIO << 0))
 
-/* CLK_DIV_DMC1 */
-#define DPM_RATIO		0x1
-#define DVSEM_RATIO		0x1
-#define PWI_RATIO		0x1
-#define CLK_DIV_DMC1_VAL	((DPM_RATIO << 24) \
-				| (DVSEM_RATIO << 16) \
-				| (PWI_RATIO << 8))
+#define DMCP_RATIO_OFFSET		20
+#define DMCD_RATIO_OFFSET		16
+#define DMC_RATIO_OFFSET		12
+#define DPHY_RATIO_OFFSET		8
+#define ACP_PCLK_RATIO_OFFSET		4
+#define ACP_RATIO_OFFSET		0
+
+#define CLK_DIV_DMC0_VAL     ((DMCP_RATIO << DMCP_RATIO_OFFSET) \
+	| (DMCD_RATIO << DMCD_RATIO_OFFSET) \
+	| (DMC_RATIO << DMC_RATIO_OFFSET) \
+	| (DPHY_RATIO << DPHY_RATIO_OFFSET) \
+	| (ACP_PCLK_RATIO << ACP_PCLK_RATIO_OFFSET) \
+	| (ACP_RATIO << ACP_RATIO_OFFSET))
+	
 
+/* CLK_DIV_DMC1 */
+#define DPM_RATIO		0x0
+#define DVSEM_RATIO		0x0
+#define C2C_ACLK_RATIO		0x1
+#define PWI_RATIO		0x0
+#define C2C_RATIO		0x1
+#define G2D_ACP_RATIO		0x0
+
+#define DPM_RATIO_OFFSET		24
+#define DVSEM_RATIO_OFFSET		16
+#define C2C_ACLK_RATIO_OFFSET		12
+#define PWI_RATIO_OFFSET		8
+#define C2C_RATIO_OFFSET		4
+#define G2D_ACP_RATIO_OFFSET		0
+
+#define CLK_DIV_DMC1_VAL ((PWI_RATIO << PWI_RATIO_OFFSET) \
+	| (C2C_RATIO << C2C_RATIO_OFFSET))
+/****************************************************************/
 /* CLK_SRC_TOP0 */
-#define MUX_ONENAND_SEL_ACLK_133	0x0
-#define MUX_ONENAND_SEL_ACLK_160	0x1
-#define MUX_ACLK_133_SEL_SCLKMPLL	0x0
-#define MUX_ACLK_133_SEL_SCLKAPLL	0x1
-#define MUX_ACLK_160_SEL_SCLKMPLL	0x0
-#define MUX_ACLK_160_SEL_SCLKAPLL	0x1
-#define MUX_ACLK_100_SEL_SCLKMPLL	0x0
-#define MUX_ACLK_100_SEL_SCLKAPLL	0x1
-#define MUX_ACLK_200_SEL_SCLKMPLL	0x0
-#define MUX_ACLK_200_SEL_SCLKAPLL	0x1
-#define MUX_VPLL_SEL_FINPLL		0x0
-#define MUX_VPLL_SEL_FOUTVPLL		0x1
-#define MUX_EPLL_SEL_FINPLL		0x0
-#define MUX_EPLL_SEL_FOUTEPLL		0x1
+#define MUX_ONENAND_SEL_ACLK_133		0x0
+#define MUX_ONENAND_SEL_ACLK_160		0x1
+#define MUX_ACLK_133_SEL_SCLKMPLL		0x0
+#define MUX_ACLK_133_SEL_SCLKAPLL		0x1
+#define MUX_ACLK_160_SEL_SCLKMPLL		0x0
+#define MUX_ACLK_160_SEL_SCLKAPLL		0x1
+#define MUX_ACLK_100_SEL_SCLKMPLL		0x0
+#define MUX_ACLK_100_SEL_SCLKAPLL		0x1
+#define MUX_ACLK_200_SEL_SCLKMPLL		0x0
+#define MUX_ACLK_200_SEL_SCLKAPLL		0x1
+#define MUX_VPLL_SEL_FINPLL			0x0
+#define MUX_VPLL_SEL_FOUTVPLL			0x1
+#define MUX_EPLL_SEL_FINPLL			0x0
+#define MUX_EPLL_SEL_FOUTEPLL			0x1
 #define MUX_ONENAND_1_SEL_MOUTONENAND	0x0
-#define MUX_ONENAND_1_SEL_SCLKVPLL	0x1
-#define CLK_SRC_TOP0_VAL		((MUX_ONENAND_SEL_ACLK_133 << 28) \
-					| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
-					| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
-					| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
-					| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
-					| (MUX_VPLL_SEL_FINPLL << 8) \
-					| (MUX_EPLL_SEL_FINPLL << 4)\
-					| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
+#define MUX_ONENAND_1_SEL_SCLKVPLL		0x1
+
+
+#define MUX_ONENAND_SEL_OFFSET		28
+#define MUX_ACLK_133_SEL_OFFSET		24
+#define MUX_ACLK_160_SEL_OFFSET		20
+#define MUX_ACLK_100_SEL_OFFSET		16
+#define MUX_ACLK_200_SEL_OFFSET		12
+#define MUX_VPLL_SEL_OFFSET		8
+#define MUX_EPLL_SEL_OFFSET		4
+#define MUX_ONENAND_1_SEL_OFFSET	0
+
+#define CLK_SRC_TOP0_VAL_RESET    	((MUX_ONENAND_SEL_ACLK_160   \
+					<< MUX_ONENAND_SEL_OFFSET) \
+	| (MUX_ACLK_133_SEL_SCLKMPLL << MUX_ACLK_133_SEL_OFFSET) \
+	| (MUX_ACLK_160_SEL_SCLKMPLL << MUX_ACLK_160_SEL_OFFSET) \
+	| (MUX_ACLK_100_SEL_SCLKMPLL << MUX_ACLK_100_SEL_OFFSET) \
+	| (MUX_ACLK_200_SEL_SCLKMPLL << MUX_ACLK_200_SEL_OFFSET) \
+	| (MUX_VPLL_SEL_FINPLL << MUX_VPLL_SEL_OFFSET) \
+	| (MUX_EPLL_SEL_FINPLL << MUX_EPLL_SEL_OFFSET)\
+	| (MUX_ONENAND_1_SEL_MOUTONENAND << MUX_ONENAND_1_SEL_OFFSET))
+	
+#define CLK_SRC_TOP0_VAL_UP_V_E_PLL ( (MUX_VPLL_SEL_FOUTVPLL   \
+					<< MUX_VPLL_SEL_OFFSET) \
+	| (MUX_EPLL_SEL_FOUTEPLL << MUX_EPLL_SEL_OFFSET))
+
 
 /* CLK_SRC_TOP1 */
-#define VPLLSRC_SEL_FINPLL	0x0
-#define VPLLSRC_SEL_SCLKHDMI24M	0x1
-#define CLK_SRC_TOP1_VAL	(VPLLSRC_SEL_FINPLL)
+#define MUX_ACLK_400_MCUISP_SUB_SEL_FINPLL		0x0 //APLL?
+#define MUX_ACLK_400_MCUISP_SUB_SEL_DIVOUT_ACLK_400_MCUISP	0x1
+#define MUX_ACLK_200_SUB_SEL_FINPLL			0x0
+#define MUX_ACLK_200_SUB_SEL_DIVOUT_ACLK_200		0x1
+#define MUX_ACLK_266_GPS_SUB_SEL_FINPLL			0x0
+#define MUX_ACLK_266_GPS_SUB_SEL_DIVOUT_ACLK_266_GPS	0x1
+#define MUX_MPLL_USER_SEL_T_FINPLL			0x0
+#define MUX_MPLL_USER_SEL_T_SCLKMPLLL			0x1
+#define MUX_ACLK_400_MCUISP_SEL_SCLKMPLL_USER_T	0x0
+#define MUX_ACLK_400_MCUISP_SEL_SCLKAPLL		0x1
+#define MUX_ACLK_266_GPS_SEL_SCLKMPLL_USER_T		0x0
+#define MUX_ACLK_266_GPS_SEL_SCLKAPLL			0x1
+
+#define MUX_ACLK_400_MCUISP_SUB_SEL_OFFSET		24
+#define MUX_ACLK_200_SUB_SEL_OFFSET			20
+#define MUX_ACLK_266_GPS_SUB_SEL_OFFSET			16
+#define MUX_MPLL_USER_SEL_T_OFFSET			12
+#define MUX_ACLK_400_MCUISP_SEL_OFFSET			8
+#define MUX_ACLK_266_GPS_SEL_OFFSET			4
+
+#define CLK_SRC_TOP1_VAL	\
+	(MUX_MPLL_USER_SEL_T_SCLKMPLLL << MUX_MPLL_USER_SEL_T_OFFSET)
+
+/* CMU_TOP
+freq(SCLK_EPLL)		= 416MHz   P=3 M=104 S=1
+freq(SCLK_VPLL)		= 440MHz   P=3 M=110 S=1
+freq(SCLKMPLL_USER_T)	=
+freq(SCLK_USBPHY0)	=
+freq(SCLK_HDMIPHY)	=
+freq(SCLK_HDMI24M)	=
+freq(ACLK_400_MCUISP)	=
+freq(ACLK_200)		= 160MHz
+freq(ACLK_266_GPS)	= 266MHz
+freq(ACLK_100)		= 100MHz
+freq(ACLK_160)		= 160MHz
+freq(ACLK_133)		= 133MHz
+freq(SCLK_ONENAND)	= 160MHz
+*/
 
 /* CLK_DIV_TOP */
+#define ACLK_400_MCUISP_RATIO	0x0
+#define ACLK_266_GPS_RATIO	0x0
 #define ONENAND_RATIO		0x0
 #define ACLK_133_RATIO		0x5
 #define ACLK_160_RATIO		0x4
 #define ACLK_100_RATIO		0x7
 #define ACLK_200_RATIO		0x3
-#define CLK_DIV_TOP_VAL		((ONENAND_RATIO << 16)	\
-				| (ACLK_133_RATIO << 12)\
-				| (ACLK_160_RATIO << 8)	\
-				| (ACLK_100_RATIO << 4)	\
-				| (ACLK_200_RATIO << 0))
+
+#define ACLK_400_MCUISP_RATIO_OFFSET		24
+#define ACLK_266_GPS_RATIO_OFFSET		20
+#define ONENAND_RATIO_OFFSET			16
+#define ACLK_133_RATIO_OFFSET			12
+#define ACLK_160_RATIO_OFFSET			8
+#define ACLK_100_RATIO_OFFSET			4
+#define ACLK_200_RATIO_OFFSET			0
+
+#define CLK_DIV_TOP_VAL	((ONENAND_RATIO << ONENAND_RATIO_OFFSET)	\
+	| (ACLK_133_RATIO << ACLK_133_RATIO_OFFSET)	\
+	| (ACLK_160_RATIO << ACLK_160_RATIO_OFFSET)	\
+	| (ACLK_100_RATIO << ACLK_100_RATIO_OFFSET)	\
+	| (ACLK_200_RATIO << ACLK_200_RATIO_OFFSET))
+/****************************************************************/
 
 /* CLK_SRC_LEFTBUS */
+#define MUX_MPLL_USER_SEL_L_FINPLL	0x0
+#define MUX_MPLL_USER_SEL_L_FOUTMPLL	0x1
 #define MUX_GDL_SEL_SCLKMPLL	0x0
 #define MUX_GDL_SEL_SCLKAPLL	0x1
-#define CLK_SRC_LEFTBUS_VAL	(MUX_GDL_SEL_SCLKMPLL)
+#define CLK_SRC_LEFTBUS_VAL	\
+	((MUX_MPLL_USER_SEL_L_FOUTMPLL << 4) \
+	|(MUX_GDL_SEL_SCLKMPLL))
+
 
 /* CLK_DIV_LEFTBUS */
 #define GPL_RATIO		0x1
 #define GDL_RATIO		0x3
 #define CLK_DIV_LEFTBUS_VAL	((GPL_RATIO << 4) | (GDL_RATIO))
 
+
 /* CLK_SRC_RIGHTBUS */
+#define MUX_MPLL_USER_SEL_R_FINPLL	0x0
+#define MUX_MPLL_USER_SEL_R_FOUTMPLL	0x1
 #define MUX_GDR_SEL_SCLKMPLL	0x0
 #define MUX_GDR_SEL_SCLKAPLL	0x1
-#define CLK_SRC_RIGHTBUS_VAL	(MUX_GDR_SEL_SCLKMPLL)
+#define CLK_SRC_RIGHTBUS_VAL	\
+	((MUX_MPLL_USER_SEL_R_FOUTMPLL << 4) \
+	|(MUX_GDR_SEL_SCLKMPLL))
+
 
 /* CLK_DIV_RIGHTBUS */
 #define GPR_RATIO		0x1
 #define GDR_RATIO		0x3
 #define CLK_DIV_RIGHTBUS_VAL	((GPR_RATIO << 4) | (GDR_RATIO))
 
+
 /* CLK_SRS_FSYS: 6 = SCLKMPLL */
-#define SATA_SEL_SCLKMPLL	0
-#define SATA_SEL_SCLKAPLL	1
+#define MIPIHSI_SEL_SCLKMPLL_USER_T	0
+#define MIPIHSI_SEL_SCLKAPLL	1
 
 #define MMC_SEL_XXTI		0
 #define MMC_SEL_XUSBXTI		1
@@ -188,13 +371,14 @@
 #define MMCC2_SEL		MMC_SEL_SCLKMPLL
 #define MMCC3_SEL		MMC_SEL_SCLKMPLL
 #define MMCC4_SEL		MMC_SEL_SCLKMPLL
-#define CLK_SRC_FSYS_VAL	((SATA_SEL_SCLKMPLL << 24) \
+#define CLK_SRC_FSYS_VAL	((MIPIHSI_SEL_SCLKMPLL_USER_T << 24) \
 				| (MMCC4_SEL << 16) \
 				| (MMCC3_SEL << 12) \
 				| (MMCC2_SEL << 8) \
 				| (MMCC1_SEL << 4) \
 				| (MMCC0_SEL << 0))
 
+
 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
 /* CLK_DIV_FSYS1 */
 #define MMC0_RATIO		0xF
@@ -206,9 +390,9 @@
 				| (MMC0_PRE_RATIO << 8) \
 				| (MMC0_RATIO << 0))
 
-/* CLK_DIV_FSYS2 */
-#define MMC2_RATIO		0xF
-#define MMC2_PRE_RATIO		0x0
+/* CLK_DIV_FSYS2  MMC2=SDMMC:20MHz*/
+#define MMC2_RATIO		0x7
+#define MMC2_PRE_RATIO		0x4
 #define MMC3_RATIO		0xF
 #define MMC3_PRE_RATIO		0x0
 #define CLK_DIV_FSYS2_VAL	((MMC3_PRE_RATIO << 24) \
@@ -342,10 +526,10 @@
 					| (pdiv << 8) \
 					| (sdiv << 0))
 
-/* APLL_CON0 */
-#define APLL_MDIV		0xFA
-#define APLL_PDIV		0x6
-#define APLL_SDIV		0x1
+/* APLL_CON0 1400MHz*/ 
+#define APLL_MDIV		0xAF
+#define APLL_PDIV		0x3
+#define APLL_SDIV		0x0
 #define APLL_CON0_VAL		SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
 
 /* APLL_CON1 */
@@ -353,31 +537,31 @@
 #define APLL_AFC		0xC
 #define APLL_CON1_VAL		((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
 
-/* MPLL_CON0 */
-#define MPLL_MDIV		0xC8
-#define MPLL_PDIV		0x6
-#define MPLL_SDIV		0x1
+/* MPLL_CON0 800MHz*/
+#define MPLL_MDIV		0x64
+#define MPLL_PDIV		0x3
+#define MPLL_SDIV		0x0
 #define MPLL_CON0_VAL		SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
 
 /* MPLL_CON1 */
 #define MPLL_AFC_ENB		0x0
 #define MPLL_AFC		0x1C
-#define MPLL_CON1_VAL		((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
+#define MPLL_CON1_VAL		((MPLL_AFC_ENB << 20) | (MPLL_AFC << 0))
 
-/* EPLL_CON0 */
-#define EPLL_MDIV		0x30
+/* EPLL_CON0 416MHz*/
+#define EPLL_MDIV		0x68
 #define EPLL_PDIV		0x3
-#define EPLL_SDIV		0x2
+#define EPLL_SDIV		0x1
 #define EPLL_CON0_VAL		SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
 
 /* EPLL_CON1 */
 #define EPLL_K			0x0
 #define EPLL_CON1_VAL		(EPLL_K >> 0)
 
-/* VPLL_CON0 */
-#define VPLL_MDIV		0x35
+/* VPLL_CON0 440MHz*/
+#define VPLL_MDIV		0x6E
 #define VPLL_PDIV		0x3
-#define VPLL_SDIV		0x2
+#define VPLL_SDIV		0x1
 #define VPLL_CON0_VAL		SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
 
 /* VPLL_CON1 */
@@ -392,6 +576,7 @@
 				| (VPLL_MFR << 16) \
 				| (VPLL_K << 0))
 
+
 /* DMC */
 #define DIRECT_CMD_NOP	0x07000000
 #define DIRECT_CMD_ZQ	0x0a000000
@@ -417,10 +602,12 @@
 	unsigned memcontrol;
 	unsigned memconfig0;
 	unsigned memconfig1;
+	unsigned ivcontrol;
 	unsigned dll_resync;
 	unsigned dll_on;
 };
 
+
 /* MIU */
 /* MIU Config Register Offsets*/
 #define APB_SFR_INTERLEAVE_CONF_OFFSET	0x400
@@ -433,14 +620,14 @@
 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET	0x828
 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET	0x830
 
-#ifdef CONFIG_ORIGEN
+#if defined(CONFIG_ORIGEN) || defined(CONFIG_TINY4412)
 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
 #define APB_SFR_INTERLEAVE_CONF_VAL	0x20001507
 #define APB_SFR_ARBRITATION_CONF_VAL	0x00000001
 #endif
 
 #define INTERLEAVE_ADDR_MAP_START_ADDR	0x40000000
-#define INTERLEAVE_ADDR_MAP_END_ADDR	0xbfffffff
+#define INTERLEAVE_ADDR_MAP_END_ADDR	0x7fffffff
 #define INTERLEAVE_ADDR_MAP_EN		0x00000001
 
 #ifdef CONFIG_MIU_1BIT_INTERLEAVED
@@ -469,10 +656,10 @@
 #define CTRL_ZQ_MODE_NOTERM	(0x1 << 0)
 #define CTRL_ZQ_START		(0x1 << 1)
 #define CTRL_ZQ_DIV		(0 << 4)
-#define CTRL_ZQ_MODE_DDS	(0x7 << 8)
+#define CTRL_ZQ_MODE_DDS	(0x4 << 8)
 #define CTRL_ZQ_MODE_TERM	(0x2 << 11)
 #define CTRL_ZQ_FORCE_IMPN	(0x5 << 14)
-#define CTRL_ZQ_FORCE_IMPP	(0x6 << 17)
+#define CTRL_ZQ_FORCE_IMPP	(0x2 << 17)
 #define CTRL_DCC		(0xE38 << 20)
 #define ZQ_CONTROL_VAL		(CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
 				| CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
@@ -497,37 +684,37 @@
 				| DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
 				| RD_FETCH | TIMEOUT_LEVEL0)
 
-#define CLK_STOP_DISABLE	(0 << 1)
-#define DPWRDN_DISABLE		(0 << 2)
+#define CLK_STOP_DISABLE	(0 << 0)
+#define DPWRDN_DISABLE		(0 << 1)
 #define DPWRDN_TYPE		(0 << 3)
 #define TP_DISABLE		(0 << 4)
 #define DSREF_DIABLE		(0 << 5)
 #define ADD_LAT_PALL		(1 << 6)
 #define MEM_TYPE_DDR3		(0x6 << 8)
 #define MEM_WIDTH_32		(0x2 << 12)
-#define NUM_CHIP_2		(1 << 16)
+#define NUM_CHIP_1		(0 << 16)
 #define BL_8			(0x3 << 20)
 #define MEMCONTROL_VAL		(CLK_STOP_DISABLE | DPWRDN_DISABLE\
 				| DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
 				| ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
-				| NUM_CHIP_2 | BL_8)
+				| NUM_CHIP_1 | BL_8)
 
 
 #define CHIP_BANK_8		(0x3 << 0)
-#define CHIP_ROW_14		(0x2 << 4)
+#define CHIP_ROW_15		(0x3 << 4)
 #define CHIP_COL_10		(0x3 << 8)
 #define CHIP_MAP_INTERLEAVED	(1 << 12)
-#define CHIP_MASK		(0xe0 << 16)
+#define CHIP_MASK		(0xc0 << 16)
 #ifdef CONFIG_MIU_LINEAR
 #define CHIP0_BASE		(0x40 << 24)
 #define CHIP1_BASE		(0x60 << 24)
 #else
-#define CHIP0_BASE		(0x20 << 24)
-#define CHIP1_BASE		(0x40 << 24)
+#define CHIP0_BASE		(0x40 << 24)
+#define CHIP1_BASE		(0x80 << 24)
 #endif
-#define MEMCONFIG0_VAL		(CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
+#define MEMCONFIG0_VAL		(CHIP_BANK_8 | CHIP_ROW_15 | CHIP_COL_10\
 				| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
-#define MEMCONFIG1_VAL		(CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
+#define MEMCONFIG1_VAL		(CHIP_BANK_8 | CHIP_ROW_15 | CHIP_COL_10\
 				| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
 
 #define TP_CNT			(0xff << 24)
@@ -555,11 +742,17 @@
 
 #define CONTROL2_VAL		0x00000000
 
-#ifdef CONFIG_ORIGEN
+
+#define IV_ON			(0x1 << 31)
+#define IV_SIZE			(0x1F << 0)
+#define IVCONTROL_VAL		(IV_ON | IV_SIZE)
+
+
+#ifdef CONFIG_TINY4412
 #define TIMINGREF_VAL		0x000000BB
-#define TIMINGROW_VAL		0x4046654f
-#define	TIMINGDATA_VAL		0x46400506
-#define	TIMINGPOWER_VAL		0x52000A3C
+#define TIMINGROW_VAL		0x6946654f
+#define	TIMINGDATA_VAL		0x46460506
+#define	TIMINGPOWER_VAL		0x5200183c
 #else
 #define TIMINGREF_VAL		0x000000BC
 #ifdef DRAM_CLK_330

4.4. 修改文件arch/arm/mach-exynos/Makefile，如下：

@@ -13,6 +13,7 @@
 obj-$(CONFIG_EXYNOS5)	+= clock_init_exynos5.o
 obj-$(CONFIG_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
 obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
+obj-$(CONFIG_EXYNOS4412)+= dmc_init_exynos4412.o clock_init_exynos4412.o
 obj-y	+= spl_boot.o tzpc.o
 obj-y	+= lowlevel_init.o
 endif

4.5. 修改文件arch/arm/mach-exynos/lowlevel_init.c，如下：

@@ -220,12 +220,12 @@
 #ifdef CONFIG_DEBUG_UART
 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
     !defined(CONFIG_SPL_BUILD)
-		exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+		exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
 		debug_uart_init();
 #endif
 #endif
 		mem_ctrl_init(actions & DO_MEM_RESET);
-		tzpc_init();
+		/*tzpc_init();*/
 	}
 
 	return actions & DO_WAKEUP;

4.5. 修改文件arch/arm/mach-exynos/spl_boot.c

这个文件包含了spl模式下加载uboot到DRAM的相关功能函数。修改如下：

@@ -7,7 +7,6 @@
 #include <config.h>
 #include <init.h>
 #include <log.h>
-
 #include <asm/cache.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
@@ -17,6 +16,8 @@
 #include <asm/arch/power.h>
 #include <asm/arch/spl.h>
 #include <asm/arch/spi.h>
+#include <debug_uart.h>
+
 
 #include "common_setup.h"
 #include "clock_init.h"
@@ -224,8 +225,13 @@
 		break;
 #endif
 	case BOOT_MODE_SD:
+#if defined(CONFIG_TINY4412)
+		offset = UBOOT_START_OFFSET;
+		size = UBOOT_SIZE_BLOC_COUNT;
+#else
 		offset = BL2_START_OFFSET;
 		size = BL2_SIZE_BLOC_COUNT;
+#endif
 		copy_bl2 = get_irom_func(MMC_INDEX);
 		break;
 #ifdef CONFIG_SUPPORT_EMMC_BOOT

到此已完成了最起码的配置，uboot已经可以编译成功了。可以尝试执行make，如果有错误，估计是某些软件没有安装，按照错误进行寻找，一般都可以找到。

执行如下命令编译：

make distclean

make tiny4412_defconfig

make

到这里，我编译完之后显示如下：

五、sd卡烧录

接下来把sd_fuse这个软件包添加到uboot的根目录下，sd_fuse这个软件我进行了一些修改，请参见《tiny4412 uboot 2020.10版本移植系列（二）——下载uboot及对uboot移植的构想和准备工作》3.3节。

进入sd_fuse目录，执行一次make, 编译出mkbl2。然后再进入sd_fuse/tiny4412目录。

把sd卡装入USB读卡器，插进电脑。比如linux主机/dev 目录下显示sd卡为设备/dev/sdd(或者别的，用fdisk -l 查看)。可以执行如下命令进行烧录：

sudo ./sd_fusing.sh /dev/sdd

这个命令把E4412_N.bl1.bin，bl2.bin(由spl/u-boot-spl.bin软件通过处理得到)，u-boot.bin三个镜像烧录到sd卡对应的位置。关于烧录的更多细节，请参看《tiny4412 uboot 2020.10版本移植系列（二）——下载uboot及对uboot移植的构想和准备工作》

用fast_fuse.sh脚本，仅烧录bl2.bin和u-boot.bin。

六、打开串口工具查看uboot启动情况

<debug_uart>
Simple Memory test start...
write 0x12345678 ...
addr:0x40000000--data:0x12345678
addr:0x50000000--data:0x12345678
addr:0x60000000--data:0x12345678
addr:0x70000000--data:0x12345678
write 0x89abcdef ...
addr:0x4ffffffc--data:0x89abcdef
addr:0x5ffffffc--data:0x89abcdef
addr:0x6ffffffc--data:0x89abcdef
addr:0x7ffffffc--data:0x89abcdef
Memory test end.



U-Boot 2020.10 (Oct 22 2020 - 17:55:32 +0800) for TINY4412

CPU:   Exynos4412 @ 1.4 GHz
Model: Tiny4412(v1412) board based on Exynos4412
Modified by Liu Guichao<gccb@foxmail.com>
DRAM:  1 GiB
WARNING: Caches not enabled
MMC:   SAMSUNG SDHCI: 0
Loading Environment from MMC... MMC Device 2 not found
*** Warning - No MMC card found, using default environment

Hit any key to stop autoboot:  0
MMC: no card present
MMC: no card present
Wrong Image Format for bootm command
ERROR: can't get kernel image!
TINY4412 #

这里打开了uart debug 相关配置，并对内存进行了简单的测试，最终可以运行到TINY4412 #，说明了uboot已经在DDR3 SDRAM上跑起来了。接下来需要针对各个功能进行修改，优化。