Verilog在ISE上的编译错误及警告

ERROR:Xst:871 - "string.v" line 19: Invalid use of input signal <out> as target.

可能是在assign语句中将input型的wire变量放在的assign语句的左端引发报错，查看自己wire的input/output定义是否出错。

WARNING:Xst:737 - Found 4-bit latch for signal <nexState>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

警告原因在于模块中的case语句和if-else语句可能并未将所有可能的值列出。如果自己已经确信全部列出或是出于某种打算这样编写，那么此警告可忽略。如果不是，检查case和if-else语句，必要时case加上default，if-else加上else。

ERROR:Xst:899 - "checkKey.v" line 27: The logic for <curState> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

出错点在图片中某处

更改为下图即可避免ERROR

具体原因请参考此处