fifo_read0

#include <sys/types.h>
#include <sys/stat.h>
#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define FIFO "/tmp/myfifo"
void  my_strupr(char *str)
{
    char *p;
   
    p = str;
    while(*p != '\0' )
    {
        if(*p >= 'a' && *p <= 'z')
        {
            *p = *p-32;
        }
        p++;
    }
}
int main(int argc,char** argv)
{
    char buf_r[100];
    int  fd;
    int  nread;
   
   
    /* 创建管道 */
    if((mkfifo(FIFO,O_CREAT|O_EXCL)<0)&&(errno!=EEXIST))
        printf("cannot create fifoserver\n");
   
    printf("Preparing for reading bytes...\n");
    memset(buf_r,0,sizeof(buf_r));
    /* 打开管道 */
    fd=open(FIFO,O_RDONLY|O_NONBLOCK,0);
    if(fd==-1)
    {
        perror("open");
        exit(1);   
    }
    while(1)
    {
        memset(buf_r,0,sizeof(buf_r));
       
        if((nread=read(fd,buf_r,100))==-1)
        {
            if(errno==EAGAIN)
                printf("no data yet\n");
        }
        my_strupr(buf_r);
        printf("read %s from FIFO\n",buf_r);
        sleep(1);
    }
    pause(); /*暂停,等待信号*/
    unlink(FIFO); //删除文件
}

``` `timescale 1ns/100ps module spi_read_ctrl( //system signal input clk_in , input clk_out, input rst_i , //cpu signal input rd_en , input rd_cs_flag , output wire [7:0] rd_data , output wire rd_data_valid , //spi bus input spi_miso , output spi_sclk , output [1:0] spi_cs_n , output spi_mosi ); //parameter list //signal list reg rd_en_reg ; reg spi_start ; reg spi_end ; reg cs_flag ; wire [7:0] spi_data_send ; wire spi_send_done ; wire [7:0] spi_data_rec ; wire spi_rec_done ; //fifo reg fifo_read_rd_en ; wire [7:0] fifo_read_dout ; wire fifo_read_full ; wire fifo_read_empty ; wire [9:0] fifo_read_rd_data_used ; wire spi_read_rst; assign spi_read_rst = rst_i ||(!rd_en) ; /////////////////////////////////////////////////////// //code begin /////////////////////////////////////////////////////// always @(posedge clk_in or posedge spi_read_rst) begin if (spi_read_rst) begin rd_en_reg <= 1'b0 ; end else begin rd_en_reg <= rd_en ; end end always @(posedge clk_in or posedge spi_read_rst) begin if (spi_read_rst) begin spi_start <= 1'b0 ; end else if (rd_en&(!rd_en_reg)) begin //rising edge,spi trans start spi_start <= 1'b1 ; end else begin spi_start <= 1'b0 ; end end always @(posedge clk_in or posedge spi_read_rst) begin if (spi_read_rst) begin spi_end <= 1'b0 ; end else if (!rd_en&rd_en_reg) begin //falling edge ,spi trans end spi_end <= 1'b1 ; end else begin spi_end <= 1'b0 ; end end always @(posedge clk_in or posedge spi_read_rst) begin if (spi_read_rst) begin cs_flag <= 1'b0 ; end else begin cs_flag <= rd_cs_flag ; end end always @(posedge clk_out or posedge spi_read_rst) begin if (spi_read_rst) begin fifo_read_rd_en <= 1'b0 ; end else if(fifo_read_rd_data_used>999) begin fifo_read_rd_en <= 1'b1 ; end else if ((fifo_read_rd_data_used<5)|fifo_read_empty) begin fifo_read_rd_en <= 1'b0 ; end else begin fifo_read_rd_en <= fifo_read_rd_en ; end end fifo_generator_read_data_0 fifo_1m_to_50m ( .rst (rst_i), // input wire rst .wr_clk (clk_in), // input wire wr_clk .rd_clk (clk_out), // input wire rd_clk .din (spi_data_rec), // input wire [7 : 0] din .wr_en (spi_rec_done&fifo_read_full), // input wire wr_en .rd_en (fifo_read_rd_en), // input wire rd_en .dout (fifo_read_dout), // output wire [7 : 0] dout .full (fifo_read_full), // output wire full .empty (fifo_read_empty), // output wire empty .rd_data_count(fifo_read_rd_data_used) ); //module inst spi_interface spi_interface_inst1( //system signal .clk (clk_in), .rst (rst_i), //custom signal .cs_flag (cs_flag), .spi_start (spi_start), .spi_end (spi_end ), .data_tx (spi_data_send ), .data_rx (spi_data_rec ), .tx_byte_done (spi_send_done ), .rx_byte_done (spi_rec_done ), //spi bus .spi_miso (spi_miso), .spi_sclk (spi_sclk), .spi_cs_n (spi_cs_n), .spi_mosi (spi_mosi) ); assign rd_data = fifo_read_dout ; assign rd_data_valid = fifo_read_rd_en ; endmodule```分析代码潜在风险
最新发布
03-18
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