Verilog刷题笔记12

题目：
You are given a module that performs a 16-bit addition. Instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes the upper 16 bits of the result, after receiving the carry-out from the first adder. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored), but the internal modules need to in order to function correctly. (In other words, the module performs 16-bit a + b + cin, while your module performs 32-bit a + b). add16add16

Connect the modules together as shown in the diagram below. The provided module has the following declaration: add16

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

我的解法：

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire [15:0]sum1;
    wire [31:16]sum2;
    wire [0:0]add;
    add16 add161(.a(a[15:0]),.b(b[15:0]),.cout(add[0:0]),.sum(sum1[15:0]));
    add16 add162(.a(a[31:16]),.b(b[31:16]),.cin(add[0:0]),.sum(sum2[31:16]));    
    assign sum={sum2,sum1};
    

endmodule

结果正确：