该文讨论了高速数字计算机中指令缓冲的工作原理，它为指令解码器提供连续的九字节指令流。由于计算机使用变长指令集，解码器会根据指令类型消耗不同数量的字节。每次消耗完指令后，移位器会移除已使用的字节并将剩余字节重新定位。空出的位置由一对预取缓冲器（IBEX, IBEX2）或虚拟指令缓存填充。这种两级预取机制允许在非关键时间进行较慢的缓存访问，避免了因等待缓存填充而使指令解码器停滞，从而确保了系统的高效运行。
摘要：
An instruction buffer of a high speed digital computer controls the flow of instruction stream to an instruction decoder. The buffer provides the decoder with nine bytes of sequential instruction stream. The instruction set used by the computer is of the variable length type, such that the decoder consumes a variable number of the instruction stream bytes, depending upon the type of instruction being decoded. As each instruction is consumed, a shifter removes the consumed bytes and repositions the remaining bytes into the lowest order positions. The byte positions left empty by the shifter are filled by instruction stream retrieved from one of a pair of prefetch buffers (IBEX, IBEX2) or from a virtual instruction cache. These prefetch buffers are arranged to hold the next two subsequent quadwords of instruction stream and provide the desired missing bytes. The IBEX prefetch buffer is filled from the instruction cache after being emptied, but prior to those particular bytes being requested to fill the instruction decoder. This two level prefetching allows the relatively slow process of cache access to be performed during noncritical time. The instruction decoder is not stalled, waiting for a cache refill, but can ordinarily obtain the desired bytes of instruction stream from the prefetch buffer.
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