Verilog HDL ，求问为什么仿真一直没有波形？

下面是代码：
//分频模块
module fenpin(rst, clk, clkk);
input rst;
input clk;
output clkk;
reg clkk;

always @(posedge clk)
if(!rst)
begin
clkk<=0;
end
else
begin
clkk<=~clkk;
end
endmodule

//选择模块
module mux(a, b, sel, y);
input a;
input b;
input sel;
output y;
reg y;

always@ *
	if(!sel) 
		y<=a;
	else 
		y<=b;

endmodule

//彩灯控制模块
module color(clk, rst, q);
input clk;
input rst;
output [7:0] q;
reg [7:0] q;
reg [5:0] s;

always @(posedge clk)
if (!rst)
s <= 6’b000000;
else
begin
if (s == 6’b111111)
s <= 6’b000000;
else
s <= s + 6’b000001;
case (s)
///////////第一种花形
6’b000000 :
q <= 8’b00000000;

        6'b000001 :
           q <= 8'b10001000;
        6'b000010 :
           q <= 8'b11001100;
        6'b000011 :
           q <= 8'b11