基于FPGA+MIG+AXI4实现DDR3 SDRAM读写操作（附代码）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;



entity img_data_gen is
	generic(
			IMG_WIDTH 	: integer := 640;
			IMG_HIGH	: integer := 512
	
	);
    port ( 
			clk 		: in 		std_logic;
			rst 		: in 		std_logic;
			
			fval 		: buffer 	std_logic;
			lval 		: inout 	std_logic;
			dval 		: out 		std_logic;
			pixel_clk 	: out 		std_logic;
			pixel_data 	: inout 	std_logic_vector(13 downto 0)
	);
end img_data_gen;

architecture Behavioral of img_data_gen is

	signal fval_cnt			: std_logic_vector(7  downto 0) := (others => '0');
	signal v_cnt			: std_logic_vector(9  downto 0) := (others => '0');
	signal h_cnt			: std_logic_vector(9  downto 0) := (others => '0');
	signal frame_cnt		: std_logic_vector(18 downto 0) := (others => '0');
	signal lval_start_flag 	: std_logic := '0';
	signal lval_dly1 		: std_logic := '0';
	signal lval_dly2 		: std_logic := '0';
	signal lval_rise 		: std_logic := '0';
	signal lval_down 		: std_logic := '0';
	signal fval_dly1 		: std_logic := '0';
	signal fval_rise 		: std_logic := '0';
	signal img_shift 		: std_logic := '0';


begin


	process(clk,rst)
	begin
		if rst = '1' then
			lval_start_flag <= '0';
		elsif rising_edge (clk) then
			if frame_cnt >= 3 and frame_cnt <= 332794 then
				lval_start_flag <= '1';
			else
				lval_start_flag <= '0';
			end if;
		end if;
	end process;

	process(clk,rst)
	begin
		if rst = '1' or fval = '0' then
			v_cnt <= (others => '0');
		elsif rising_edge (clk) then
			if lval_start_flag = '1' and v_cnt <= 648 then
				v_cnt <= v_cnt + 1;
			elsif v_cnt = 649  then					
				v_cnt <= (others => '0');			
			end if;
		end if;
	end process;
	
	process(clk,rst)
	begin
		if rst = '1' then
			lval <= '0';
		elsif rising_edge (clk) then
			if v_cnt >= 1 and v_cnt <= IMG_WIDTH  then						
				lval <= '1';
			else
				lval <= '0';												
			end if;
		end if;
	end process;
	

	process(clk,rst)
	begin
		if rst = '1' then
			lval_dly1 	<= '0';
			lval_dly2 	<= '0';
		elsif rising_edge (clk) then
			lval_dly1	<= lval;
		    lval_dly2   <= lval_dly1;	
		end if;
	end process;
	
	lval_rise <= lval_dly1 and (not lval_dly2);
	lval_down <= (not lval_dly1) and lval_dly2;

	process(clk,rst)
	begin
		if rst = '1' or fval = '0' then
			h_cnt <= (others => '0');
		elsif rising_edge (clk) then
			if lval_rise = '1' then
				h_cnt <= h_cnt + 1;
				if h_cnt = 512 then
					h_cnt <= (others => '0');
				end if;
			else
				h_cnt <= h_cnt;
			end if;
		end if;
	end process;
	

	
	process(clk,rst)										--产生一张静态图像
	begin
		if rst = '1' then
			pixel_data <= (others => '0');		
		elsif rising_edge (clk) then
			if lval = '1' then
				pixel_data <= pixel_data + 1;			
			else
				pixel_data <= (others => '0');			
			end if;
		end if;
	end process;


--------------------------------------------生成场同步信号--------------------------------	
	process(clk,rst)
	begin
		if rst = '1' then
			frame_cnt <= (others => '0');
		elsif rising_edge (clk) then
			frame_cnt <= frame_cnt + 1;
			if frame_cnt = 400000 then			
				frame_cnt <= (others => '0');
			end if;
		end if;
	end process;
			  
	process(clk,rst)
	begin
		if rst = '1' then
			fval <= '0';
		elsif rising_edge (clk) then
			if frame_cnt >= 0 and frame_cnt <= 332794 then		
				fval <= '1';
			else
				fval <= '0';
			end if;
		end if;
	end process;
	
---------------------------------------场同步信号计数--------------------------------
	

	process(clk,rst)
	begin
		if rst = '1' then
			fval_dly1 <= '0';
		elsif rising_edge (clk) then
			fval_dly1 <= fval;
		end if;
	end process;
	
	fval_rise <= fval and (not fval_dly1);	
	
	process(clk,rst)
	begin
		if rst = '1' then
			fval_cnt <= (others => '0');
		elsif rising_edge (clk) then
			if fval_rise = '1' then
				fval_cnt <= fval_cnt + 1;
			elsif fval_cnt = 200 then
				fval_cnt <= (others => '0');
			else
				fval_cnt <= fval_cnt;
			end if;
		end if;
	end process;
	
	process(clk,rst)
	begin
		if rst = '1' then
			
		elsif rising_edge (clk) then
			if fval_cnt>= 0 and  fval_cnt< 100 then
				img_shift <= '0';
			elsif fval_cnt >= 100 and fval_cnt <= 200 then
				img_shift <= '1';
			end if;
		end if;
	end process;
	
----------------------------------------生成像素时钟------------------------------
	pixel_clk <= clk;
	
	dval <= lval;

end Behavioral;