Closed Bug 1984782 Opened 2 months ago Closed 1 month ago

Optimize riscv64 InsertBits function for pos=0

Categories

(Core :: JavaScript Engine: JIT, enhancement, P5)

RISCV64
All
enhancement

Tracking

()

RESOLVED FIXED
144 Branch
Tracking Status
firefox144 --- fixed

People

(Reporter: parisoplop, Assigned: parisoplop)

References

(Blocks 1 open bug)

Details

Attachments

(1 file)

The MacroAssemblerRiscv64::InsertBits function is sometimes called with pos==0. In these cases, instead of constructing a mask, the bits in the dest and source can be cleared with shifts.

OS: Unspecified → All
Hardware: Unspecified → RISCV64

Working on this

Assignee: nobody → parisoplop
Status: UNCONFIRMED → ASSIGNED
Ever confirmed: true
Blocks: sm-masm
Severity: -- → S4
Priority: -- → P5
Severity: S4 → N/A

@nbp how do I get someone to take a look at this? Thanks.

(In reply to parisoplop from comment #3)

@nbp how do I get someone to take a look at this? Thanks.

One way is to set a needinfo (Request information from) field of bugzilla, which is below the comment box.
I guess Julian might not have notice the phabricator notification, otherwise we should find a better reviewer.

Tomorrow, I will clean-up the rest of RISCV bugs, such that these bugs are easier to find by the person who are concerned with maintaining this backend.

Flags: needinfo?(jseward)
Status: ASSIGNED → RESOLVED
Closed: 1 month ago
Resolution: --- → FIXED
Target Milestone: --- → 144 Branch
Flags: needinfo?(jseward)
QA Whiteboard: [qa-triage-done-c145/b144]
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