Maxime Marini

the Acer has become the first to unveil a laptop powered by Intel Corporation’s #18A based #PantherLake processor, despite ongoing questions about 18A’s production timeline and yield stability. Unveiled at IFA 2025 in Berlin, Acer’s Swift 16 AI, features Panther Lake and targets the ultrathin premium market. It’s Acer’s first 16-inch laptop under 1kg and will launch in 2026. It includes a 3K OLED display, 120Hz refresh rate, up to 32GB LPDDR5X RAM, Wi-Fi 7, Bluetooth 6, and Thunderbolt 4. Panther Lake marks Intel’s renewed push for efficient, high-performance mobile chips using its 18A node. This marks a strategic shift, as previous mobile chips like #LunarLake relied on TSMC. If 18A proves successful in Panther Lake, it could validate Intel Foundry turnaround plan and restore confidence in its roadmap execution. Intel CFO David Zinsner recently confirmed that Panther Lake remains on track. The first chips will ship by end-2025, with more in early 2026. #ClearwaterForest, a #Xeon chip also built on 18A, is expected in mass production by 2026. 📘 MY NEW BOOK RELEASED! 🌍 the Global Chip War   the Global Chip War, uncovers the fierce battle between countries and global companies to control chip technology. This book explains why these tiny chips matter to your life, economy, and future—making it a must-read for anyone who wants to understand tomorrow’s world. 🛒 Grab your copy now on Amazon Kindle!👉 https://lnkd.in/gQxiT7qZ For a deeper understanding of the latest semiconductor technologies, read my book, Semiconductor For All 👉 https://lnkd.in/gzVV2fJm , To explore how chips shape our world and industries, subscribe my YouTube channel, https://lnkd.in/gdksSJG2

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UBM (Under Bump Metallization) Purpose: UBM is a critical layer in advanced semiconductor packaging, enabling reliable electrical and mechanical connections between the chip and solder bumps or copper pillars. Functions: Provides electrical interconnection, wetting for solder, diffusion barrier, and mechanical support. Prevents failures like delamination, solder voids, and electromigration. Applications: Used in Flip-Chip, Wafer-Level Packaging (WLP), Fan-Out WLP, 2.5D/3D IC stacking, and high-end 3D packaging (e.g., HBM, CoWoS). Materials: Multi-layer stacks: adhesion (Ti, TiW, Ta), seed/conductor (Cu), barrier (TiN, Ta, Ni), wetting (Au, Ag), and solder (Sn, SnAgCu). Etching: Selective etchants are used for each metal layer (e.g., HF+H₂O₂ for Ti, H₃PO₄+H₂O₂ for Cu, KI/I₂ for Au). Process control is crucial to avoid over-etching and ensure pad accuracy. Trends: Moving toward finer pitches (<50 μm), eco-friendly chemistries, cost reduction (less Au), and dry/plasma etching for better precision. Conclusion: UBM is foundational for next-gen semiconductor reliability, yield, and performance, especially as packaging becomes more complex and dense.

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Ever wonder what solar panels could do if they had brains? That’s basically what HTEC and Infineon Technologies pulled off. Their AI-powered system, running on Infineon’s PSOC™ Edge platform, uses real-time voltage, current, and temperature data to tweak power output on the fly—no fancy irradiance sensors needed. ⚡ 23× faster response 🔋 42× less energy used 🔧 Built-in predictive maintenance Smarter energy. Less waste. More uptime. This is the kind of tech that moves us forward. Curious how it works? 🔗 Check out the whitepaper: https://lnkd.in/gKqhM_F4

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Is There Still A Future For Hard Disk Drives? The cost of HDDs and SSDs will continue to fall, while capacity will continue to increase in both. The capacity for solid state drives (#SSDs) keeps going up while the price per terabyte keeps falling, sometimes raising questions about the future for hard disk drives (#HDDs). Will the cost of #SSDs per TB eventually become so low that they will totally displace HDDs? Barry Pangrle decided to ask a couple of experts in the field, Jim Handy from Objective Analysis and Thomas Coughlin of Coughlin Associates. He was looking for a comparison projection for HDDs and SSDs that would go about five years out into the future. Jim had performed such an exercise back in 2017, WDC: No SSD/HDD Crossover,but I needed something more recent. Jim had his SSD forecast data, shown in red in Figure 1 and Tom provided the HDD data shown in blue. The slope is steeper for the #SSD data, but it does not look like we’ll see a crossover in the next 5 years. The green $4.75/TB point was placed there by Barry to show readers where that falls on the plot and to use again later in another chart.... A very big thank you to Barry Pangrle , Jim Handy , Thomas Coughlin and Semiconductor Engineering for this very interesting full comparison/article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eKTxfR7P #semiconductorindustry #semiconductor #technology #tech #chip #chips #it #datacenter #technology #memory #storage #computer #ssd #hdd

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🤝 STMicroelectronics and Morse Micro will be hosting a live joint webinar on 17 September 2025 on how to unlock #IoT 2.0 with Wi-Fi #HaLow and #STM32. 💡 In this webinar, ST and Morse Micro will deep dive into the MM6108-EKH05-05US, a powerful Wi-Fi HaLow (IEEE 802.11ah) development board purpose-built for a wide range of IoT applications. Combining Morse Micro’s #MM6108 Wi-Fi HaLow chip with ST’s advanced components, including the #STM32U5 ultra-low-power MCU, BlueNRG-M2 Bluetooth® module, and the #IIS328DQ 3-axis accelerometer, this development board is ready to power smart cities, industrial monitoring, building automation, and more. Key topics/learnings: ----------------------- 🌟 What defines IoT 2.0 and, more importantly, why traditional wireless tech is no longer enough 🌟 Why Wi-Fi HaLow is the key to long-range, high-throughput IoT 2.0 applications 🌟 ST's role is supporting next gen IoT development and platforming 🌟 How to get started with the MM6108-EKH05-05US dev board for rapid prototyping (whether you’re designing a next-gen asset tracker or a connected environmental sensor) 🌟 Application examples across industrial, smart building, and urban IoT use cases (e.g. camera) Register today via https://lnkd.in/gDksyUxq

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Resistive RAM, or ReRAM is an interesting type of non volatile memory. I just learnt that it can store analog values! That makes it interesting not just for digital flash type storage, but for analog neural network models too. In July, while attending the #FSiC conference at IHP, I got the chance to talk to Emilio Pérez-Bosch Quesada about his ReRAM research. In this video you’ll get an explanation of how ReRAM works, how it’s being tested at IHP and even see a short demo of it in action. Thanks again to IHP for the opportunity to visit and meet the scientists and engineers that make semiconductors possible. 🎥 https://lnkd.in/dcSKBEea #semiconductor #reram

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Big News in the Semiconductor Industry Axcelis Technologies (Nasdaq: ACLS) and Veeco Instruments (Nasdaq: VECO) are joining forces in a transformational all-stock merger, creating a new $4.4B leader in semiconductor capital equipment. Together, we’ll deliver: ✅ A diversified product portfolio across ion implantation, laser annealing, ion beam deposition, advanced packaging, and MOCVD. ✅ Expanded R&D scale to fuel next-generation technologies for customers. ✅ A resilient financial profile, with strong cash flow to drive organic growth and shareholder returns. ✅ Greater access to secular growth markets, including AI and power solutions, with a combined addressable market of $5B+. With complementary expertise and innovative teams, the combined company will be the 4th largest U.S. wafer fabrication equipment supplier by revenue, positioned to accelerate technology roadmaps and unlock new opportunities for customers worldwide. The merger is expected to be accretive to non-GAAP EPS in the first year post-close and deliver $35M in annual cost synergies within 24 months. Tune in today at 8:30 AM ET for our joint webcast as we share more on this exciting new chapter. Together, Axcelis + Veeco = a stronger partner for innovation, growth, and customer success. Thanks to Yahoo Finance for providing the full article with additional background, charts, and insights at the link below. 👇 https://lnkd.in/gEfnKVRs #Semiconductors #Innovation #Growth #Technology #Axcelis #Veeco

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Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK. TT-Ascalon is Tenstorrent’s high-performance RISC-V CPU, built on open standards to provide maximum flexibility and architectural control. It is based on the open RISC-V ISA and is RVA23 compliant. A central focus of the Ashling–Tenstorrent collaboration is comprehensive trace support, built on the RISC-V standard N-Trace architecture. RiscFree integrates with Tenstorrent’s Ascalon CPUs to capture detailed trace data across multi-core systems, enabling real-time visibility into instruction execution, memory transactions, and key system events. In addition to N-Trace, Tenstorrent’s Debug Signal Trace (DST) infrastructure has been fully implemented in its Ascalon CPUs, providing access to critical micro-architectural signals alongside standard trace data during post-silicon validation. DST enhances debugging, performance analysis, and coverage, and is fully supported by Ashling’s RiscFree tools—enabling deep trace visibility with minimal integration overhead. Learn more here: https://lnkd.in/gthF_9uj #RISCVEverwhere #DEBUG #Tenstorrent

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