Tomas Sluka

Introducing our new paper: "ZKProphet – Understanding Performance of Zero-Knowledge Proofs on GPUs", to appear at the IEEE International Symposium on Workload Characterization (IISWC 2025) this month in Irvine, California. Zero-Knowledge Proofs (ZKPs) are one of the most fascinating ideas in modern cryptography. They let someone prove that a statement is true—without revealing why it’s true or how they know it. Using a ZKP, you could prove you’re over 21 without ever showing your date of birth or ID. The verifier learns only that your claim is valid—nothing else. That’s the magic of a ZKP. Our paper, ZKProphet, takes a deep look at what it actually takes to make these computationally intensive proofs fast and practical on today’s GPUs. ZKPs rely on two computational workhorses: Multi-Scalar Multiplication (MSM) and the Number-Theoretic Transform (NTT). While past research has supercharged MSM, our analysis shows that NTT is now the growing bottleneck—accounting for up to 90% of total proof generation time. We also find that: 🔹 ZKP workloads are limited by GPU integer throughput, not memory latency or bandwidth. 🔹 No single MSM/NTT implementation dominates—performance depends on problem scale. 🔹 Future acceleration will come from smarter use of GPU parallelism and memory, not just adding more hardware. ZKProphet offers the first detailed performance roadmap for scaling ZKPs on GPUs—a step toward making privacy-preserving, verifiable computing truly practical. This paper was joint work with Tarunesh Verma, Yichao Yuan, and Nishil Talati. I’ll be attending IISWC 2025 next week in Irvine, where my PhD student Tarunesh Verma will present this work. I'm looking forward to connecting with colleagues at the conference! You can download the full paper here: https://lnkd.in/dijcaMpX #iiswc2025 #zkp #cryptography #hardwaresecurity

177

1 Kommentar

Davide Asnaghi and Lenny Khazan started Diode Computers with a question: why does hardware design still move so slowly? Drawing on their backgrounds in software and electrical engineering, they set out to reframe circuit board design as a software problem. One that AI could help solve. They went from building a tool to catch design mistakes to creating an end-to-end AI-powered system that generates production-ready boards. Along the way, they discovered that most companies didn’t want a better tool — they wanted the whole solution. That insight led to rapid growth, real customers, and over 100 boards designed in just a few months, all by a two-person team. And this week, they announced $11.4M in Series A funding led by a16z. YC Partner Diana Hu recently sat down with the founders to talk about how they got here, their founding story, and the kind of company they are building. This is the story of two engineers trying to make hardware move at software speed, and the infrastructure making it possible. https://lnkd.in/gahNjw52

407

17 Kommentare

THE STRATEGY BEHIND NanoOCM AS ITALIAN PhotonPath Raises €5.1M Series A. The ECOC Exhibition 2025 in Copenhagen closed its doors today. One of the most compelling stories came from Optica corporate member PhotonPath, an Italian scale-up I had the chance to visit during the exhibition. Founded in 2019 as a spin-off from Politecnico di Milano and nurtured in PoliHub, PhotonPath is building what many in our industry have been waiting for: scalable integrated photonics with real-world applications across telecom, datacenters, and sensing. CEO and co-founder Douglas Aguiar, explains how their journey began: “Our research focused on integrated photonics and ultra-low-noise electronics the building blocks of the photonic circuits we now commercialise.” That focus has translated into products such as the NanoOCM Spectrum Analyzer—the world’s smallest high-resolution optical spectrum analyzer with <1W power consumption—and a reconfigurable optical platform (Spectre) for precise fiber-optic sensing in harsh environments. What impressed me most is PhotonPath’s strategy during the interview: * Not just chasing speed, but solving the complex parts of the optical layer where electronics alone can’t deliver. * Bridging telecom with industrial sensing: from high-voltage grid monitoring in the Netherlands to temperature and stress sensors co-developed with an automotive braking systems manufacturer. * A fabless model aligned with the next wave of applications in datacenter interconnects (together with Telefónica) and software-defined optical networks. With €5.1M in Series A funding, PhotonPath is now scaling up manufacturing of its proprietary chipsets and plug-and-play modules—pushing Europe closer to a tipping point where integrated photonics meets mass-market demand. 🌍 From Milan to Copenhagen, PhotonPath shows how Europe’s early photonics research is finally converging with commercial opportunity. Onward to ECOC 2026, which will be held in Malaga. What a coincidence!

71

3 Kommentare

⚡🔬Menhir Photonics has opened a state-of-the-art ultrafast laser facility in Zurich, scaling production of femtosecond sources. This investment underscores the rising demand for precision lasers... 👉 Read the full story on Electro Optics: https://lnkd.in/ewu_uRSU Florian Emaury / Anan Dai / Amir Nejadmalayeri / Daniel Gilks #UltrafastLasers #PhotonicsIndustry #Quantum #MedTech (Image: Menhir Photonics)

45

1 Kommentar

Fundamental Fridays: Edge Couplers In the rapidly evolving world of photonics, one challenge remains constant: efficiently getting light on and off a photonic integrated circuit (PIC). Whether you’re building ultra-fast data center links, precision sensing systems, or next-generation LiDAR, the interface between fiber and chip can make or break system performance. Enter the fiber-to-chip edge coupler. A small but critical component designed to bridge the gap between an optical fiber and a waveguide on the chip’s edge. Unlike grating couplers, which couple light from above the chip surface, edge couplers connect at the chip perimeter, enabling ultra-low insertion loss, broadband operation, and high-power handling. Why Edge Couplers Matter. The push toward co-packaged optics (CPO), high-performance computing (HPC), and 800G+ optical interconnects demands optical interfaces that are: ↗️ Low loss: Every decibel counts in reducing power consumption and extending reach. ↗️ Scalable: Compatible with high-volume assembly for commercial deployment. ↗️ Broadband: Supporting multiple wavelength bands for flexible system design. ↗️ Robust: Ready for real-world environments in telecom, automotive, aerospace, and medical applications. Edge couplers are driving advancements across multiple industries: ↗️ Telecommunications & Data Centers: Supporting ever-faster optical transceivers and CPO architectures. ↗️ Automotive & LiDAR: Delivering stable optical connections for autonomous navigation systems. ↗️ Aerospace & Defense: Providing rugged, high-performance optical links in mission-critical systems. ↗️ Biophotonics & Healthcare: Enabling precise coupling in optical coherence tomography (OCT) and lab-on-chip devices. ↗️ Quantum Photonics: Connecting quantum chips to long-distance fiber networks for secure communications. The Design Challenge Designing edge couplers isn’t as simple as aligning fiber to waveguide. Engineers must optimize mode matching, spot-size conversion, and taper geometry while accounting for fabrication tolerances, thermal effects, and polarization performance. Accurate optical simulation is essential to minimize design iterations, reduce costs, and accelerate time-to-market. Let's tackle these challenges together to create smarter, smaller optic and photonic systems. Join us for the Ansys Optics Virtual Deep Dive: Fiber-to-Chip Coupling Solutions for Co-Packaged Optics on August 21, where our experts will walk through simulation workflows, performance optimization strategies, and packaging considerations for next-generation photonic systems. 📅 Register now: Ansys Optics Virtual Deep Dive – Fiber-to-Chip Coupling Solutions for Co-Packaged Optics https://ansys.me/416g3BP #SynopsysAnsys #Photonics #EdgeCoupler #CoPackagedOptics #PIC #OpticalInterconnects

43

SILICON PHOTONICS VALUE CHAIN FOR CO-PACKAGED OPTICS Overview of the Value Chain The value chain progresses from the initial design and component manufacturing to packaging, equipment integration, and finally to the end customers utilizing Co-Packaged Optics (CPO) technology Stages and Key Players 1. Optical Engines / PIC design: This stage focuses on designing the Photonic Integrated Circuits (PICs) that are central to silicon photonics - Scale-out: Companies like NVIDIA, Broadcom, Marvell, Ranovus, Coherent, Lumentum, and Fujitsu are involved in designing PICs for scaling out optical interconnects - Scale-up: Broadcom, AyarLabs, Intel, Marvell, NVIDIA, Nubis, IBM, Avicena, and AttoTude focus on designing PICs for scaling up capabilities 2. Lasers/microLED: This stage involves the development and manufacturing of light sources for silicon photonics - CW-DFB: Lumentum, Broadcom, Coherent, Sivers, POET, Intel, Scintil, Molex, Open Light, Cisco, Sicoya, MACOM, Newphotonics, DenseLight, Ennostar, Furukawa Electric, Lightmatter, and Casela are key players in CW-DFB laser technology - Quantum dot: Lumentum, Innolume, Intel, ARC, QD Laser are prominent in quantum dot laser development - Comb: Xscape Photonics, Pilot Photonics, Luminar, Enlightra are working on comb lasers - microLED: Lightmatter, Casela, Avicena, Intel, Tetra, Ennostar, and Lumileds are involved in microLED technology 3. ASIC/XPU partners: These are partners involved in designing and integrating Application-Specific Integrated Circuits (ASICs) or other processing units with photonic components - Notable companies include NVIDIA, Broadcom, Marvell, AMD, Intel, Mediatek, Alchip, and Lightmatter 4. Foundries and fabs: This stage involves the fabrication of silicon photonic components and integrated circuits - Leading foundries and fabs include GlobalFoundries, Silterra, TSMC, Tower, Intel, UMC, SMIC, NTT, IMECAS - Additionally, R&D institutions like Leti, IMEC, AIM Photonics, ITRI are crucial for innovation in this area 5. Packaging/System assembling/Testing: This crucial stage involves integrating and testing the various photonic and electronic components into functional systems - Key players include ASE Holdings, Foxconn, Fabrinet, Winstek, Cisco, Jabil, JCET, MEC, Dell Technologies, StatsChipPAC, Eviden, FormFactor, Teradyne, Amkor, Samsung, and Wistron 6. CPO Equipment (AI server or switch): This segment deals with the equipment that incorporates CPO technology, such as AI servers and network switches - Companies like NVIDIA, Micas, Delta, Juniper, Ruijie, H3C, Oracle, Tencent, ByteDance, Inventec, Pegatron, QCT, Wiwynn, Lenovo, and others are key in this area 7. End Customers: These are the ultimate users of CPO-enabled systems and equipment - Major end customers include AWS, Azure, Meta, IBM, Google, and Hewlett Packard Enterprise, representing hyperscale data centers and cloud service providers Image Source - Yole

37