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ORCIDCODES 1999: Rome, Italy
- Ahmed Amine Jerraya, Luciano Lavagno, Frank Vahid:
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, CODES 1999, Rome, Italy, 1999. ACM 1999, ISBN 1-58113-132-1 - Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik
:
Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. 2-6 - Michael Gschwind:
Instruction set selection for ASIP design. 7-11 - Margarida F. Jacome, Gustavo de Veciana, Cagdas Akturan:
Resource constrained dataflow retiming heuristics for VLIW ASIPs. 12-16 - Kayhan Küçükçakar:
An ASIP design methodology for embedded systems. 17-21 - Marnix Arnold, Henk Corporaal:
Automatic detection of recurring operation patterns. 22-26 - François Charot, Vincent Messé:
A flexible code generation framework for the design of application specific programmable processors. 27-31 - Pieter van der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees A. Vissers:
An MPEG-2 decoder case study as a driver for a system level design methodology. 33-37 - Dirk Desmet, Michiel Esvelt, Prabhat Avasare, Diederik Verkest, Hugo De Man:
Timed executable system specification of an ADSL modem using a C++ based design environment: a case study. 38-42 - Tomás Bautista, Antonio Núñez:
Flexible design of SPARC cores: a quantitative study. 43-47 - François Clouté, Jean-Noël Contensou, Daniel Esteve, Pascal Pampagnin, Philippe Pons, Yves Favard:
Hardware/software co-design of an avionics communication protocol interface system: an industrial case study. 48-52 - Philippe Coste, Fabiano Hessel, P. LeMarrec, Zoltan Sugar, Mohamed Romdhani, Rodolph Suescun, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
Multilanguage design of heterogeneous systems. 54-58 - Frank Vahid, Tony Givargis:
The case for a configure-and-execute paradigm. 59-63 - H. J. H. N. Kenter, Claudio Passerone, W. J. M. Smits, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli:
Designing digital video systems: modeling and scheduling. 64-68 - François Pogodalla, Richard Hersemeule, Pierre Coulomb:
Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuse. 69-73 - Thierry Grandpierre, Christophe Lavarenne, Yves Sorel:
Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors. 74-78 - Francis G. Wolff, Michael J. Knieser, Daniel J. Weyer, Christos A. Papachristou:
Using codesign techniques to support analog functionality. 79-84 - Marcello Lajolo, Mihai T. Lazarescu, Alberto L. Sangiovanni-Vincentelli:
A compilation-based software estimation scheme for hardware/software co-simulation. 85-89 - Tao Zhou, Xiaobo Sharon Hu, Edwin Hsing-Mean Sha:
A probabilistic performance metric for real-time system design. 90-94 - Zhao Wu, Wayne H. Wolf:
Iterative cache simulation of embedded CPUs with trace stripping. 95-99 - Sungjoo Yoo, Kiyoung Choi:
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages. 100-104 - Donald E. Thomas, JoAnn M. Paul, Simon N. Peffers, Sandra J. Weber:
Peer-based multithreaded executable co-specification. 105-109 - Pao-Ann Hsiung:
Timing coverification of concurrent embedded real-time systems. 110-114 - Felice Balarin:
Worst-case analysis of discrete systems based on conditional abstractions. 115-119 - Jianwen Zhu, Daniel Gajski:
A unified formal model of ISA and FSMD. 121-125 - Ansgar Bredenfeld:
Co-design tool construction using APICES. 126-130 - Peter Voigt Knudsen, Jan Madsen:
Graph based communication analysis for hardware/software codesign. 131-135 - Ingo Sander, Axel Jantsch:
System synthesis utilizing a layered functional model. 136-140 - Jean-Yves Brunel, Erwin A. de Kock, W. M. Kruijtzer, H. J. H. N. Kenter, W. J. M. Smits:
Communication refinement in video systems on chip. 142-146 - Stephen A. Edwards:
Compiling Esterel into sequential code. 147-151 - William Fornaciari, Donatella Sciuto, Cristina Silvano:
Power estimation for architectural exploration of HW/SW communication on system-level buses. 152-156 - Yung-Hsiang Lu, Tajana Simunic, Giovanni De Micheli:
Software controlled power management. 157-161 - I. D. Bates, E. Graeme Chester, David J. Kinniment:
A statechart based HW/SW codesign system. 162-166 - Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya:
3D exploration of software schedules for DSP algorithms. 168-172 - Karsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich:
Scheduling hardware/software systems using symbolic techniques. 173-177 - Paul Pop, Petru Eles, Zebo Peng:
Scheduling with optimized communication for time-triggered embedded systems. 178-182 - Hyunok Oh, Soonhoi Ha:
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling. 183-187 - Jan Madsen, Peter Bjørn-Jørgensen:
Embedded system synthesis under memory constraints. 188-192 - David L. Rhodes, Wayne H. Wolf:
Overhead effects in real-time preemptive schedules. 193-197 - Jones Albuquerque, Claudionor José Nunes Coelho Jr., Carlos Frederico Cavalcanti, Diógenes Cecilio da Silva Jr., Antônio Otávio Fernandes:
System-level partitioning with uncertainty. 198-202 - Dinesh Ramanathan, Ali Dasdan, Rajesh K. Gupta:
Timing-driven HW/SW codesign based on task structuring and process timing simulation. 203-207 - Jonas Plantin, Erik Stoy:
Aspects of system-level design. 209-210 - Mark Genoe, Christopher K. Lennard, Joachim Kunkel, Brian Bailey, Gjalt G. de Jong, Grant Martin, M. M. Kamal Hashmi, Shay Ben-Chorin, Anssi Haverinen:
How standards will enable hardware/software co-design. 211-212
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