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ORCID16th ISQED 2015: Santa Clara, California, USA
- Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015. IEEE 2015, ISBN 978-1-4799-7581-5
Session 1A: Robust Memory Design
- James Boley, Benton H. Calhoun:
Stack based sense amplifier designs for reducing input-referred offset. 1-4 - Farah B. Yahya, Mohammad M. Mansour, James W. Tschanz, Muhammad M. Khellah
:
Designing low-VTh STT-RAM for write energy reduction in scaled technologies. 5-9 - Roohollah Yarmand, Behzad Ebrahimi, Hassan Afzali-Kusha, Ali Afzali-Kusha, Massoud Pedram:
High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors. 10-17 - Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
An energy-efficient on-chip memory structure for variability-aware near-threshold operation. 23-28
Session 1B: Advances in Physical Design & Optimization
- Jun Yong Shin, Fadi J. Kurdahi, Nikil D. Dutt:
Thermal sensor allocation for SoCs based on temperature gradients. 29-34 - Hyungjung Seo, Jeongwoo Heo, Taewhan Kim:
Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing. 35-39 - George Gonzalez, Murari Mani, Mahesh Sharma:
Large-scale multi-corner leakage optimization under the sign-off timing environment. 40-45 - Xing Huang, Wenzhong Guo, Guolong Chen:
Fast obstacle-avoiding octilinear steiner minimal tree construction algorithm for VLSI design. 46-50 - Chiung-Chih Ho, Hsin-Pei Tsai, Liang-Chi Lai, Rung-Bin Lin:
A router for via configurable structured ASIC with standard cells and relocatable IPs. 51-56
Session 1C: Manufacturing, Modeling, and Design Issues in Nanoscale CMOS
- Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov:
Circuit design perspectives for Ge FinFET at 10nm and beyond. 57-60 - Chieh-Yang Chen, Wen-Tsung Huang, Yiming Li:
Electrical characteristic and power consumption fluctuations of trapezoidal bulk FinFET devices and circuits induced by random line edge roughness. 61-64 - Meeta Srivastav, Leyla Nazhandali:
Study of the impact of aging on many-core energy-efficient DSP systems. 66-70 - Shuo Wang, Yue Gao, Melvin A. Breuer:
GlYFF: A framework for global yield and floorplan aware design optimization. 70-76 - Jon Nafziger, Dan Burggraf:
Method for efficient flash bit cell current compression in deeply erased bits. 77-81
Session 2A: Voltage Regulators and Analog Design
- Nijad Anabtawi, Rony Ferzli:
A simplified single-inductor dual-output DC-DC buck converter architecture with a fully digital Σ-Δ based controller. 82-85 - Tae-Jin Chung, Kwang Sub Yoon:
A CMOS hysteretic DC-DC buck converter with a low output ripple voltage. 86-89 - Govardhana Rao Talluri, K. K. Rakesh, Maryam Shojaei Baghini:
A 4-14 Gbps inductor-less adaptive linear equalizer using hybrid filter in 65 nm CMOS technology. 90-97 - Kaushik Mazumdar, Steven Bartling, Sudhanshu Khanna, Mircea R. Stan:
A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU. 98-102 - Seok Min Jung, Janet Meiling Roveda:
A radiation-hardened-by-design phase-locked loop using feedback voltage controlled oscillator. 103-106 - Yucai Wang, Vamsy P. Chodavarapu:
Design of a sigma-delta modulator in standard CMOS process for wide-temperature applications. 107-111
Session 2B: Architectural Analysis and Algorithms
- Zheng Wang, Liu Yang, Anupam Chattopadhyay:
Architectural reliability estimation using design diversity. 112-117 - Jianmo Ni, Nan Wang, Takeshi Yoshimura:
Tabu search based multiple voltage scheduling under both timing and resource constraints. 118-122 - Lan Wu, Wei Zhang:
Cache-aware SPM allocation algorithms for hybrid SPM-cache architectures. 123-129 - Marco P. Stefani, Thais Webber, Ramon Fernandes, Rodrigo Cataldo, Leticia B. Poehls, César A. M. Marcon:
Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs. 130-134 - Zijian Hou, Xin Chen, Weifeng He:
Improved pipeline data flow for DySER-based platform. 135-140 - Shen Feng, Chris Driscoll, Jerediah R. Fevold, Hao Jiang, Gunar Schirner:
Rapid heterogeneous prototyping from Simulink. 141-146
Session 2C: BIST and Scan Testing
- Gustavo K. Contreras, Yang Zhao, Nisar Ahmed, LeRoy Winemberg, Mohammad Tehranipoor:
LBIST pattern reduction by learning ATPG test cube properties. 147-153 - Panagiotis Sismanoglou, Vlasis Pitsios, Dimitris Nikolos:
Preemptive built-in self-test for in-field structural testing. 154-161 - Sungyoul Seo, Yong Lee, Joohwan Lee, Sungho Kang:
A scan shifting method based on clock gating of multiple groups for low power scan testing. 162-166 - Subramanian Chebiyam, Anshuman Chandra, Rohit Kapur:
Designing effective scan compression solutions for industrial circuits. 167-172 - Hyunyul Lim, Wooheon Kang, Sungyoul Seo, Yong Lee, Sungho Kang:
Low power scan bypass technique with test data reduction. 173-176 - Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko:
Incremental ATPG methods for multiple faults under multiple fault models. 177-180
Session 3A: Low Power Circuit Design
- Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera:
Energy reduction by built-in body biasing with single supply voltage operation. 181-185 - Jihai Duan, Qiangyu Hao, Yu Zheng, Baolin Wei, Weilin Xu, Shichao Xu:
Design of an incoherent IR-UWB receiver front-end in 180-nm CMOS technology. 186-190 - Mohammad Saber Golanbari, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani R. Nassif:
Analysis and optimization of flip-flops under process and runtime variations. 191-196 - Nourhan M. Bahgat, DiaaEldin S. Khalil, Salwa H. El-Ramly:
Energy efficient design of DVB-T2 constellation demapper. 197-200 - Srivatsan Chellappa, Chandarasekaran Ramamurthy, Vinay Vashishtha, Lawrence T. Clark:
Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation. 201-206
Session 3B: Energy and Power Management for IoT
- Menglong Guan, Lei Wang:
Temperature aware refresh for DRAM performance improvement in 3D ICs. 207-211 - Wenjie Huang, Lei Wang:
Adaptive tracking channel control for GNSS receivers under renewable energy. 212-216 - Mahmoud Elbayoumi, Michael S. Hsiao, Mustafa ElNainay:
Novel SAT-based invariant-directed low-power synthesis. 217-222 - Hend Affes, Amal Chaker, Michel Auguin:
Application and OS unconscious power manager for SoC systems. 223-226 - Nga Dang, Hossein Tajik, Nikil D. Dutt, Nalini Venkatasubramanian, Eli Bozorgzadeh:
Orchestrated application quality and energy storage management in solar-powered embedded systems. 227-233
Session 3C: Low-power and Robust Design Techniques
- Mohammad Saeed Abrishami, Alireza Shafaei, Yanzhi Wang, Massoud Pedram:
Optimal choice of FinFET devices for energy minimization in deeply-scaled technologies. 234-238 - Saraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka:
Ultra-fast variability-aware optimization of mixed-signal designs using bootstrapped kriging. 239-242 - Tianqi Wang, Liyi Xiao, Mingxue Huo, Chunhua Qi, Shanshan Liu:
Novel technique for P-hit single-event transient mitigation using enhance dummy transistor. 243-249 - Sharad Bagri, Kelson Gent, Michael S. Hsiao:
Signal domain based reachability analysis in RTL circuits. 250-256 - Tun Li, Jian Hu, Yang Guo, Sikun Li, QingPing Tan:
Equivalence checking of scheduling in high-level synthesis. 257-262
Poster Session
- Luv Tomar, Saurabh Gupta, Raghuvir Tomar, Prakash Bhartia:
Design and analysis of low pass microstrip filters using MATLAB. 263-266 - Yakup Murat Mert, Osman Seckin Simsek:
Employing dynamic body-bias for short circuit power reduction in SRAMs. 267-271 - Taizhi Liu, Chang-Chih Chen, Linda S. Milor:
Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splines. 272-279 - Alireza Shafaei, Yanzhi Wang, Antonio Petraglia, Massoud Pedram:
Design optimization of sense amplifiers using deeply-scaled FinFET devices. 280-283 - Jarbas Silveira, Mathieu Bodin, Joao Marcelo Ferreira, Alan Cadore Pinheiro, Thais Webber, César A. M. Marcon:
A fault prediction module for a fault tolerant NoC operation. 284-288 - Anirban Sengupta, Saumya Bhadauria:
User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis. 289-292 - Xinsheng Wang, Wenpan Liu, Mingyan Yu:
A distinctive O(mn) time algorithm for optimal buffer insertions. 293-297 - Jae-Won Jang, Swaroop Ghosh:
Design and analysis of novel SRAM PUFs with embedded latch for robustness. 298-302 - Chao Deng, Yici Cai, Qiang Zhou:
Fast synthesis of low power clock trees based on register clustering. 303-309 - Zhen Meng, Song Chen, Lu Huang:
Irregularly shaped voltage islands generation with hazard and heal strategy. 310-315 - Lihua Liang, Yuanxiang Zhang, Richard Rao:
Impact of geometry parameter on electromigration reliability in FCBGA package. 316-321 - Hailang Wang, Emre Salman:
Enhancing system-wide power integrity in 3D ICs with power gating. 322-326 - SheXiao Xuan, Y. Yang:
Temperature-aware thread assignment of many-core processor. 332-336 - Maya H. Safieddine, Rouwaida Kanj, Fadi A. Zaraket, Ali S. Elzein, Mohamad Jaber:
Separation of concerns for hardware components of embedded systems in BIP. 337-344 - Luke Pierce, Spyros Tragoudas:
Unreachable code identification for improved line coverage. 345-351
Session 4A: Challenges in SOC Design
- Rajat Chauhan, Prajkta Vyavahare, Siva Kothamasu:
Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power. 357-360 - Ming Fan, Qiushi Han, Shuo Liu, Gang Quan:
On-line reliability-aware dynamic power management for real-time systems. 361-365 - Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard:
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. 366-370 - Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand:
Efficient static D-latch standard cell characterization using a novel setup time model. 371-378 - Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney Laert Vilar Calazans:
TDTB error detecting latches: Timing violation sensitivity analysis and optimization. 379-383
Session 4B: Network and Multiprocessing Systems
- Zhaohui Cyril Yuan, Rong Zhu, Yiqin Cao, Guifen Jiang:
Adaptive mode assignment in performance-critical cyber-physical systems. 384-391 - Marcelo Mandelli, Luciano Ost, Gilles Sassatelli, Fernando Gehm Moraes:
Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliability. 392-396 - Dharanidhar Dang, Biplab Patra, Rabi N. Mahapatra:
A 2-layer laser multiplexed photonic network-on-chip. 397-401 - Hao Wen, Wei Zhang:
Exploring shared memory and cache to improve GPU performance and energy efficiency. 402-405 - Karthi Duraisamy, Ryan Gary Kim, Partha Pratim Pande:
Enhancing performance of wireless NoCs with distributed MAC protocols. 406-411
Session 4C: Verification and Delay Measurement
- Miroslav N. Velev, Chaoqiang Zhang, Ping Gao, Alex David Groce:
Exploiting abstraction, learning from random simulation, and SVM classification for efficient dynamic prediction of software health problems. 412-418 - Jomu George Mani Paret, Otmane Aït Mohamed:
Optimum domain partitioning to increase functional verification coverage. 419-423 - Yao Chen, Andrew B. Kahng, Bao Liu, Wenjun Wang:
Crosstalk-aware signal probability-based dynamic statistical timing analysis. 424-429 - Kentaroh Katoh, Kazuteru Namba:
A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement. 430-434 - Woosung Lee, Keewon Cho, Jooyoung Kim, Sungho Kang:
Near optimal repair rate built-in redundancy analysis with very small hardware overhead. 435-439
Session 5A: Hardware and System Security
- Md Tanvir Arafin, Carson Dunbar, Gang Qu, Nathan R. McDonald, L. Yan:
A survey on memristor modeling and security applications. 440-447 - Teng Xu, Miodrag Potkonjak:
Digital PUF using intentional faults. 448-451 - Jude Angelo Ambrose, Roshan G. Ragel, Darshana Jayasinghe, Tuo Li, Sri Parameswaran:
Side channel attacks in embedded systems: A tale of hostilities and deterrence. 452-459 - Jaya Dofe, Connor Reed, Ning Zhang, Qiaoyan Yu:
Fault-tolerant methods for a new lightweight cipher SIMON. 460-464 - Cheng-Wei Lin, Swaroop Ghosh:
Novel self-calibrating recycling sensor using Schmitt-Trigger and voltage boosting for fine-grained detection. 465-469 - Yanbo Niu, Anping Jiang:
The low power design of SM4 cipher with resistance to differential power analysis. 470-474
Session 5B: Systems Implementation and Optimization
- Yu Cai, Ken Mai, Onur Mutlu:
Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks. 475-484 - Liyi Xiao, Jiaqiang Li, Jie Li, Jing Guo:
Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories. 485-489 - Florin Balasa, Noha Abuaesh, Ilie I. Luican, Hongwei David Zhu:
Scratch-pad memory banking by dynamic programming for embedded data-intensive applications. 490-494 - Samir Zampiva, Carlos Moratelli, Fabiano Hessel:
A hypervisor approach with real-time support to the MIPS M5150 processor. 495-501 - Prateek Pendyala, Vijaya Sankara Rao Pasupureddi:
RT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data rate. 502-506 - Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi:
Low power scheduling in high-level synthesis using dual-Vth library. 507-511
Session 5C: Packaging and 3D Integration
- Gary Brist, John Park:
A novel approach to IC, package and board co-optimization. 512-518 - Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa:
An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs. 519-523 - Daniel P. Seemuth, Azadeh Davoodi, Katherine Morrow:
Automatic die placement and flexible I/O assignment in 2.5D IC design. 524-527 - Hailang Wang, Emre Salman:
Resource allocation methodology for through silicon vias and sleep transistors in 3D ICs. 528-532 - Surajit Kumar Roy, Kaustav Roy, Chandan Giri, Hafizur Rahaman:
Recovery of faulty TSVs in 3D ICs. 533-536 - Seungwon Kim, Seokhyung Kang, Ki Jin Han, Youngmin Kim:
Novel adaptive power gating strategy of TSV-based multi-layer 3D IC. 537-541
Session 6A: Sensor Technology
- Brandon Rumberg, David W. Graham:
A low-power field-programmable analog array for wireless sensing. 542-546 - Paul Leons, Aryan Yaghoubian, Glenn E. R. Cowan, Jelena Trajkovic, Yvon Nazon, Samar Abdi:
On improving the range of inductive proximity sensors for avionic applications. 547-551 - Chun-Kai Chang, Chung-Hsin Su, Yung-Hua Kao, Ming-Hung Yu, Thilo Sauter, Paul C.-P. Chao:
A new single inductor bipolar multiple output (SIBMO) boost converter using pulse frequency modulation (PFM) control for OLED drivers and optical transducers. 552-555 - Deivid Antunes Tesch, Everton Luís Berz, Fabiano Hessel:
RFID indoor localization based on Doppler effect. 556-560 - Chun-An Huang, Li-Chuang, Kim Hsu, Steel Chung, Tim Chan:
A novel physical failure analysis of MEMS motion sensor for interface inspection. 561-564
Session 6B: EDA for Design Exploration & Analysis Beyond Moore's Law
- Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan:
Exploring memory controller configurations for many-core systems with 3D stacked DRAMs. 565-570 - Spandana Rachamalla, Arun Joseph, Rahul M. Rao, Diwesh Pandey:
Virtual logic netlist: Enabling efficient RTL analysis. 571-576 - Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh:
A logic difference generator with spare cells consideration for ECO synthesis. 577-580 - Abdalrahman M. Arafeh, Sadiq M. Sait:
Cells reconfiguration around defects in CMOS/nanofabric circuits using simulated evolution heuristic. 581-588 - Hsin-Ju Chang, Yen-Lung Chen, Conan Yeh, Chien-Nan Jimmy Liu:
Layout-aware analog synthesis environment with yield consideration. 589-593
Session 6C: Emerging Solid-State Device and Interconnect Technologies
- Pankaj Kumar Pal, Brajesh Kumar Kaushik, B. Anand, S. Dasgupta:
A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives. 594-598 - Chenyun Pan, Praveen Raghavan, Francky Catthoor, Zsolt Tokei, Azad Naeemi:
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. 599-603 - Karthik Yogendra, Mei-Chin Chen, Xuanyao Fong, Kaushik Roy:
Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter. 604-609 - Ya-Chi Huang, Meng-Hsueh Chiang, Wei-Chou Hsu, Shiou-Ying Cheng:
6-T SRAM performance assessment with stacked silicon nanowire MOSFETs. 610-614 - Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Partially depleted silicon-on-ferroelectric insulator field effect transistor (PD-SOFFET). 615-619
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