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ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 30
Volume 30, Number 1, 2025
- Quan Zhou
, Si Cai, Jianjun Li, Yi Gao, Zhi Qu, Tao Jin:
Deadline and Period Assignment for Guaranteeing Timely Response of the Cyber-Physical System. 1-26 - Dina Hussein, Taha Belkhouja, Ganapati Bhat, Jana Doppa:
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices. 1-27 - Guiqi Mo, Yimin Xia, Jianhong Ou, Shuting Cai, Xiaoming Xiong:
Layout Congestion Prediction Based on Regression-ViT. 1-21 - Shiyuan Huang, Fangxin Liu, Tian Li, Zongwu Wang, Ning Yang, Haomin Li, Li Jiang:
STCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization. 1-22 - Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang:
Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators. 1-34 - Anna Bernasconi, Valentina Ciriani, Jordi Cortadella, Marco Costa, Tiziano Villa:
Area-driven Boolean bi-decomposition by function approximation. 1-21 - Irith Pomeranz:
SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan. 1-13 - Sonam Sharma, Dipanjan Roy, Digambar Pawar:
PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis. 1-34
Volume 30, Number 2, March 2025
- Noel Daniel Gundi, Sanghamitra Roy, Koushik Chakraborty:
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience. 16:1-16:25 - Donghao Fang, Boyang Zhang, Hailiang Hu, Wuxi Li, Bo Yuan, Jiang Hu:
Global Placement Exploiting Soft 2D Regularity. 17:1-17:21 - Xiaoman Yang, Haibao Chen, Yuhan Zhang, Tianshu Hou, Pengpeng Ren, Runsheng Wang, Zhigang Ji, Ru Huang:
Physics-Informed Learning Based Multiphysics Simulation for Fast Transient TSV Electromigration Analysis. 18:1-18:22 - Srijeeta Maity, Anirban Majumder, Rudrajyoti Roy, Ashish R. Hota, Soumyajit Dey:
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms. 19:1-19:32 - Zhihao Xu, Shikai Guo, Xiaochen Li, Zun Wang, He Jiang:
SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation. 20:1-20:25 - Chenyi Wen, Haonan Du, Jiayi Wang, Zhengrui Chen, Li Zhang, Qi Sun, Cheng Zhuo:
PACE: A Piece-Wise Approximate Floating-Point Divider with Runtime Configurability and High Energy Efficiency. 21:1-21:23 - Gaoyang Zhao, Junzhong Shen, Rongzhen Lin, Hua Li, Yaohua Wang:
ISOAcc: In-situ Shift Operation-based Accelerator For Efficient in-SRAM Multiplication. 22:1-22:24 - Nikolaos Ioannis Deligiannis, Tobias Faller, Josie Esteban Rodriguez Condia, Riccardo Cantoro, Bernd Becker, Matteo Sonza Reorda:
Enhancing the Effectiveness of STLs for GPUs via Bounded Model Checking. 23:1-23:24 - Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar:
HEANA: A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference. 24:1-24:37 - Muhammad Rashedul Haq Rashed, Sven Thijssen, Sumit Jha, Rickard Ewetz:
LOGIC: Logic Synthesis for Digital In-Memory Computing. 25:1-25:27 - Stéphane Pouget, Louis-Noël Pouchet, Jason Cong:
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. 26:1-26:44 - Guoqing Li, Rengang Li, Tuo Li, Tinghuan Chen, Meng Zhang, Henk Corporaal:
Algorithm-Hardware Co-design for Accelerating Depthwise Separable CNNs. 27:1-27:22 - Jinchao Chen, Yang Wang, Ying Zhang, Yantao Lu, Qing Li, Qiuhao Shu:
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems. 28:1-28:25 - Yi-Ting Lin, Kang-Ting Fan, Iris Hui-Ru Jiang:
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process. 29:1-29:17 - Huayang Cai, Pengcheng Huang, Genggeng Liu, Xing Huang, Yidan Jing, Wenhao Liu, Ting-Chi Wang:
SPTA 2.0: Enhanced Scalable Parallel Track Assignment Algorithm with Two-Stage Partition Considering Timing Delay. 30:1-30:23 - Yuhao Zhou, Jianhui Jiang, Zhenxue He, Ying Zhang, Chengcheng Chen, Zhanhui Shi, Wei Zhang, Keying Yang:
An Efficient Area and Reliability Optimization Method for MPRM Circuits Based on High-dimensional Genetic Algorithm. 31:1-31:22 - Yike Zhou, Yanyan Jiang, Jian Lu:
Unveiling Cross-checking Opportunities in Verilog Compilers. 32:1-32:23 - Juan-David Guerrero-Balaguera, Josie Esteban Rodriguez Condia, Matteo Sonza Reorda:
Effective Fault Effects Evaluation for Permanent Faults in GPUs executing DNNs. 33:1-33:33
Volume 30, Number 3, May 2025
- Jingyu Pan, Guanglei Zhou, Chen-Chia Chang, Isaac Jacobson, Jiang Hu, Yiran Chen:
A Survey of Research in Large Language Models for Electronic Design Automation. 34:1-34:21
- Charles Gouert, Nektarios Georgios Tsoutsos:
Data Privacy Made Easy: Enhancing Applications with Homomorphic Encryption. 35:1-35:31 - Sallar Ahmadi-Pour, Sangeet Saha, Klaus D. McDonald-Maier, Rolf Drechsler:
MESSI: Task Mapping and Scheduling Strategy for FPGA-based Heterogeneous Real-Time Systems. 36:1-36:29 - Sandeep Sunkavilli, Nishanth Goud Chennagouni, Qiaoyan Yu:
A New Dynamic Countermeasure to Strengthen Design Obfuscation in FPGAs. 37:1-37:25 - Wenxue Wu, Tong Zhang, Zhen Li, Xiaoqin Feng, Liwei Zhang, Fengyuan Ren:
Dynamic Per-Flow Queues in Shared Buffer TSN Switches. 38:1-38:21 - Aastha Gupta, Ravi Sindal, Vaibhav Neema:
Secure & Reliable 10T SRAM Cell during Read, Write and Hold Operations against Power Analysis Attack. 39:1-39:19 - Cong Jiang, Haoyang Sun, Dan Feng, Zhiyao Xie, Benjamin Tan, Kang Liu:
LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization. 40:1-40:25 - Harsh Sharma, Pratyush Dhingra, Jana Doppa, Ümit Y. Ogras, Partha Pratim Pande:
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models. 41:1-41:24 - Xingwei Feng, Yifan Xu, Zhangcheng Huang, Wuyi Xu, Zhaori Bi, Fan Yang, Xuan Zeng, Ye Lu:
Hierarchical Integration of Reinforcement Learning and Optimization Algorithms for Time-Efficient Design Automation of Complex Analog Circuit. 42:1-42:22 - Liwei Zhang, Tong Zhang, Xiaoqin Feng, Yanying Ma, Hao Yang, Fengyuan Ren:
Fault-Tolerant Cyclic Queuing and Forwarding with Fast ACK in Time-Sensitive Networking. 43:1-43:18 - Yuang Ma, Yulong Meng, Zihao Xuan, Song Chen, Yi Kang:
HNM-CIM: An Algorithm-Hardware Co-designed SRAM-based CIM for Transformer Acceleration Exploiting Hybrid N:M Sparsity. 44:1-44:22 - Irith Pomeranz:
Test Templates to Guide Test Generation for Single-Cycle Gate-Exhaustive Faults. 45:1-45:17 - Jian Hu, Zhenlei Liu:
Context-aware Data Augmentation for Hardware Code Fault localization. 46:1-46:20 - Jiahao Xu, Zhuolun He, Shuo Yin, Yuan Pu, Wenjian Yu, Bei Yu:
EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling. 47:1-47:19 - Zhaoxu Zhou, Zihang Huang, Junwei Li, Yanjiang Liu, Zibin Dai:
CRM_BF: A Low-Overhead, High-Efficient and Reconfigurable Operation Unit Design Approach Using the Customized Reed-Muller Unit For Boolean Functions of Sequence Cipher Algorithms. 48:1-48:30 - Chunlin Li, Long Chai, Yong Zhang, Mengjie Yang, Ruidong Zhao, Zihao Zhang, Denghua Li, Shaohua Wan:
Deep Reinforcement Learning-Based Resource Allocation with Enhanced Perception and Low-Latency for Autonomous Driving in ISAC-aided VEC. 49:1-49:34 - Wenhao Liu, Yan Xing, Shuting Cai, Weijun Li, Xiaoming Xiong:
Optimizing FPGA Routing with Explainable Co-Learning of Congestion and Wirelength. 50:1-50:22 - Wei-Chun Huang, Chih-Wei Tang, Kuei-Chung Chang, Tien-Fu Chen, Hsiang-Cheng Hsieh, Ming-Hsuan Tsai:
Design Space Exploration for Scalable DNN Accelerators Using a Memory-Centric Analytical Model for HW/SW Co-Design. 51:1-51:29
Volume 30, Number 4, July 2025
- Amir Hossein Jalilvand, Faeze S. Banitaba, Seyedeh Newsha Estiri, Sercan Aygun, M. Hassan Najafi:
Sorting it out in Hardware: A State-of-the-Art Survey. 52:1-52:31 - Ahmed Mahmoudi, Andrija Neskovic, Celine Thermann, Robin Sehm, Christoph Hübner, Tavia Plattenteich, Rolf Meyer, Rainer Buchty, Mladen Berekovic, Saleh Mulhem:
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains. 53:1-53:41
- Binwu Zhu, Su Zheng, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling. 54:1-54:20 - Jingui Lin, Shiyan Liang, Wenxiong Lin, Peng Gao, Yan Xing, Tingting Wu, Xiaoming Xiong, Shuting Cai:
Early Stage DRC Hotspot Prediction for Mixed-Size Designs Through an Efficient Graph-Based Deep Learning. 55:1-55:21 - Mahsa Heidari, Bijan Alizadeh:
FixRTL: Auto-correction of Multiple RTL Bugs by a New Feature Burst Clustering Algorithm and Mutation. 56:1-56:21 - Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestoras E. Evmorfopoulos, Sachin S. Sapatnekar:
An Analytical Solution for Transient Electromigration Stress in Multisegment Straight-line Interconnects Based on a Stress-wave Model. 57:1-57:31 - Ying Wang, Haopeng Yan, Yiwen Zhang, Peng Gao, Fei Yu, Xiaoming Xiong, Shuting Cai:
PSCaps: High-Performance Pose-Sensitive Layout Hotspot Detector based on CapsNet. 58:1-58:21 - Irith Pomeranz:
DTGx2: Dual Target Diagnostic Test Generation. 59:1-59:15 - Nuo Xu, Yihong Hu, Chaochao Feng, Wei Tong, Kang Liu, Liang Fang:
ILOSSS - Improved Logic Synthesis based on Several Stateful Logic Gates. 60:1-60:23 - Wenqian Zhao, Lancheng Zou, Zixiao Wang, Xufeng Yao, Bei Yu:
HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization. 61:1-61:18 - Mingxin Tang, Wei Chen, Lizhou Wu, Libo Huang, Kun Zeng:
ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.0. 62:1-62:24 - Luca Collini, Jitendra Bhandari, Chiara Muscari Tomajoli, Abdul Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato:
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction. 63:1-63:23 - Sallar Ahmadi-Pour, Sajjad Parvin, Chandan Kumar Jha, Rolf Drechsler:
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits. 64:1-64:23 - Manju Rajan, Abhijit Das, John Jose:
Securing Network-on-Chips against Trojan-Induced Packet Duplication Attacks. 65:1-65:28 - Yannick Uhlmann, Till Moldenhauer, Jürgen Scheible:
Interactive Visual Performance Space Exploration of Operational Amplifiers with Differentiable Neural Network Surrogate Models. 66:1-66:33 - Yuefei Wang, Wendong Mao, Lang Feng, Jin Sha, Zhongfeng Wang:
A CPU+FPGA OpenCL Heterogeneous Computing Platform for Multi-Kernel Pipeline. 67:1-67:23 - Po-Wei Chen, Sheng-Tan Huang, Shao-Yun Fang:
Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition. 68:1-68:21 - Yan Xing, Hongtao Hu, Weijun Li, Shuting Cai, Xiaoming Xiong:
Concurrent Prediction of Timing and wire Length Using A Multi-Task Graph Neural Network. 69:1-69:20
Volume 30, Number 5, September 2025
- Ruiyang Qin, Dancheng Liu, Chenhui Xu, Zheyu Yan, Zhaoxuan Tan, Zhenge Jia, Amir Nassereldine, Jiajie Li, Meng Jiang, Ahmed Abbasi, Jinjun Xiong, Yiyu Shi:
Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices. 70:1-70:58 - Peng Xu, Su Zheng, Mingzi Wang, Ziyang Yu, Shixin Chen, Tinghuan Chen, Keren Zhu, Tsung-Yi Ho, Bei Yu:
Rank-DSE: Neural Pareto Comparator of Microarchitecture Design Space Exploration. 71:1-71:24 - Upoma Das, Mohammad Sazadur Rahman, Akshay Kulkarni, Mark Tehranipoor, Farimah Farahmandi:
PSCMark: Power Side Channel-based Watermarking for SoC IPs Using Clock Gates. 72:1-72:27 - Christian Ewert, Andrija Neskovic, Carsten Heinz, Felix Muuss, Alexander Treff, Marc Gourjon, Rainer Buchty, Thomas Eisenbarth, Andreas Koch, Mladen Berekovic, Saleh Mulhem:
Lightweight Authenticated Integration and In-Field Secure Operation of System-in-Package. 73:1-73:23 - Yequan Zhao, Hai Li, Ian A. Young, Zheng Zhang:
Poor Man's Training on MCUs: A Memory-Efficient Quantized Back-Propagation-Free Approach. 74:1-74:33 - Phuoc Pham, Tae-Min Park, Sung-Hyuk Cho, Tayyeb Mahmood, Joon-Sung Yang, Jaeyong Chung:
AGD: Analytic Gradient Descent for Discrete Optimization in EDA and its Use to Gate Sizing. 75:1-75:22 - Xinrui Wang, Lang Feng, Yujie Wang, Taotao Xu, Yinhe Han, Zhongfeng Wang:
Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks. 76:1-76:23 - Hongyang Pan, Keren Zhu, Fan Yang, Xuan Zeng, Sen Liu, Yong Xiao, Yun Shao, Zhufei Chu:
Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis. 77:1-77:29 - Xufeng Yao, Wenqian Zhao, Qi Sun, Cheng Zhuo, Bei Yu:
High-level Synthesis Directives Design Optimization via Large Language Model. 78:1-78:24 - Aniruddha Datta, Bhanu Vikas Yaganti, Mate Palocska, Andrew Dove, Arik Peltz, Krishnendu Chakrabarty:
Test-Fleet Scheduling in Complex Validation and Production Environments. 79:1-79:32 - Zhiteng Chao, Feng Gu, Junying Huang, Wenjie Li, Jing Ye, Huawei Li, Xiaowei Li:
Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation. 80:1-80:27 - Shiyan Liang, Jingui Lin, Dongwei Liu, Wenxiong Lin, Peng Gao, Yuzhe Ma, Tingting Wu, Xiaoming Xiong, Shuting Cai:
RTMF: Routing based on TDM for Multi-FPGA System. 81:1-81:24 - Ayush Dahiya, Vansh Singhal, Poornima Mittal:
A Variation Tolerant Write Assist Read Decoupled 9T SRAM Cell for Low Voltage Application. 82:1-82:22 - Wei-Kai Liu, Benjamin Tan, Krishnendu Chakrabarty:
Patchability-Driven Design Exploration for System-on-Chip Patching Architectures. 83:1-83:21 - Xinguo Deng, Wen Xu, Mingsheng Mei, Henghui Hong, Yourun Lan, Jiarui Chen:
An Improved MCTS Algorithm for Ordered Escape Routing of Differential Pair. 84:1-84:26 - Bruno D. Miranda, Márcio Castro, Luiz Cláudio Villar dos Santos:
A Canonical Test Representation for Verification of Shared-Memory Behavior in Multiprocessor Systems. 85:1-85:22 - Jingyuan Li, Yuan Dai, Wenbo Yin, Lingli Wang:
MoDAF: A Multi-objective Divide-and-Conquer Parameter Tuning Framework for CGRAs. 86:1-86:28
- Bruno Ferres, Oussama Oulkaid, Matthieu Moy, Gabriel Radanne, Ludovic Henrio, Pascal Raymond, Mehdi Khosravian:
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits. 87:1-87:28 - Morteza Golzan, Telex M. N. Nkouatchah, Karteek Popuri, Lihong Zhang:
Analog and Mixed-Signal IC Modeling and Optimization: An Artificial Intelligence Perspective. 88:1-88:32
Volume 30, Number 6, November 2025
- Robert Paul Dick, Hammond Pearce, Li Shang, Fan Yang:
Introduction to Special Issue on Large Language Models for Electronic System Design Automation. 89:1-89:3 - Zhuolun He, Yuan Pu, Haoyuan Wu, Tairu Qiu, Bei Yu:
Large Language Models for EDA: Future or Mirage? 90:1-90:53 - Nathaniel Ross Pinckney, Christopher Batten, Mingjie Liu, Haoxing Ren, Brucek Khailany:
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation. 91:1-91:20 - Samuel Gomes Lopes, Shien Zhu, Gustavo Alonso:
Exploring Large Language Models for Hierarchical Hardware Circuit and Testbench Generation. 92:1-92:39 - Kaiyan Chang, Wenlong Zhu, Kun Wang, Xinyang He, Nan Yang, Zhirong Chen, Dantong Jin, Cangyuan Li, Yunhao Zhou, Hao Yan, Zhuoliang Zhao, Yuan Cheng, Mengdi Wang, Shengwen Liang, Yinhe Han, Xiaowei Li, Huawei Li, Ying Wang:
A data-centric chip design agent framework for Verilog code generation. 93:1-93:27 - Yichen Shi, Zhuofu Tao, Yuhao Gao, Tianjia Zhou, Cheng Chang, Yaxin Wang, Bingyu Chen, Genhao Zhang, Alvin Liu, Zhiping Yu, Ting-Jung Lin, Lei He:
AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-design Using Knowledge Graph RAG. 94:1-94:37 - E. Bhawani Eswar Reddy, Sutirtha Bhattacharyya, Ankur Sarmah, Fedrick Nongpoh, Karthik Maddala, Chandan Karfa:
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks. 95:1-95:27 - Luca Collini, Siddharth Garg, Ramesh Karri:
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap. 96:1-96:24 - Cangyuan Li, Chujie Chen, Yudong Pan, Wenjun Xu, Yiqi Liu, Kaiyan Chang, Yujie Wang, Mengdi Wang, Huawei Li, Yinhe Han, Ying Wang:
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models. 97:1-97:21 - Magi Chen, Ting-Chi Wang:
HyperPlace: Harnessing a Large Language Model for Efficient Hyperparameter Optimization in GPU-Accelerated VLSI Placement. 98:1-98:27 - Zhe Xiao, Xu He, Haoying Wu, Bei Yu, Yang Guo:
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools. 99:1-99:24 - Jason Blocklove, Shailja Thakur, Benjamin Tan, Hammond Pearce, Siddharth Garg, Ramesh Karri:
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback. 100:1-100:26 - Khushboo Qayyum, Chandan Kumar Jha, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler:
LLM-assisted Bug Identification and Correction for Verilog HDL. 101:1-101:28 - Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, Bei Yu:
HDLdebugger: Streamlining HDL debugging with Large Language Models. 102:1-102:26 - Baleegh Ahmad, Joey Ah-kiow, Benjamin Tan, Ramesh Karri, Hammond Pearce:
FLAG: Finding Line Anomalies (in RTL code) with Generative AI. 103:1-103:30 - Sujan Ghimire, Yu-Zheng Lin, Muntasir Mamun, Muhtasim Alam Chowdhury, Farhad Alemi, Shuyu Cai, Jinduo Guo, Mingyu Zhu, Honghui Li, Banafsheh Saber Latibari, Setareh Rafatirad, Pratik Satam, Soheil Salehi:
HWREx: AI-enabled Hardware Weakness and Risk Exploration and Storytelling Framework with LLM-assisted Mitigation Suggestion. 104:1-104:33 - Zhouyang Lu, Hailin Xu, Anrui Chen, Siyuan Tang, Junyi Zhang, Yifei Feng, Wentao Pan, Jiangli Huang:
HSG-RAG: Hierarchical Knowledge Base Construction for Embedded System Development. 105:1-105:21 - Yangbo Wei, Li Huang, Qi Feng, Zhanfei Chen, Jinlong Yan, Ting-Jung Lin, Zhen Huang, Kun Ren, Wei W. Xing, Lei He:
ModelGen: Automating Semiconductor Parameter Extraction with Large Language Model Agents. 106:1-106:26 - Jun S. Shim, Hyeonji Chang, Yeseong Kim, Jihong Kim:
DeepPM: Predicting Performance and Energy Consumption of Program Binaries Using Transformers. 107:1-107:27
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