Taha Soliman

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Norbert Wehn

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Publications

2025
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Luca Parrini, Anirban Kar, Benjamin Hettwer, Taha Soliman, Yogesh Singh Chauhan, Hussam Amrouch, Norbert Wehn:
A Lightweight PUF-Based Weights Obfuscation Technique for Secure In-Memory AI Inference. IEEE Trans. Circuits Syst. I Regul. Pap. 72(10): 5597-5609 (2025)
2024
[c15]
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Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn:
Error Detection and Correction Codes for Safe In-Memory Computations. ETS 2024: 1-4
[i1]
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  - journals/corr/abs-2404-09818
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Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn:
Error Detection and Correction Codes for Safe In-Memory Computations. CoRR abs/2404.09818 (2024)
2023
[c10]
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  - conf/icecsys/LaleniSPMKGKWJ23
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Nellie Laleni, Taha Soliman, Cecilia De la Parra, Franz Müller, Tobias Kirchner, Andre Guntoro, Thomas Kämpfe, Norbert Wehn, T. Jang:
Torwards Variability Immune Scalable FeFET-based Macros for IMC DNN Accelerators. ICECS 2023: 1-4
2022
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Chirag Sudarshan, Taha Soliman, Jan Lappas, Christian Weis, Mohammad Hassani Sadi, Matthias Jung, Andre Guntoro, Norbert Wehn:
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 367-380 (2022)
[j2]
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Cecilia De la Parra, Taha Soliman, Andre Guntoro, Akash Kumar, Norbert Wehn:
Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation. IEEE Micro 42(6): 17-24 (2022)
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Taha Soliman, Nellie Laleni, Tobias Kirchner, Franz Müller, Ashish Shrivastava, Thomas Kämpfe, Andre Guntoro, Norbert Wehn:
FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration. ACM Trans. Embed. Comput. Syst. 21(6): 84:1-84:25 (2022)
[c9]
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Taha Soliman, Amro Eldebiky, Cecilia De la Parra, Andre Guntoro, Norbert Wehn:
Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators. SOCC 2022: 1-6
[c8]
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  - conf/vlsi/SudarshanSKWW22
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Chirag Sudarshan, Taha Soliman, Thomas Kämpfe, Christian Weis, Norbert Wehn:
FeFET versus DRAM based PIM Architectures: A Comparative Study. VLSI-SoC 2022: 1-6
2021
[c7]
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Taha Soliman, Cecilia De la Parra, Andre Guntoro, Norbert Wehn:
Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators. AICAS 2021: 1-4
[c6]
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Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung, Norbert Wehn, Andre Guntoro:
A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. ASP-DAC 2021: 35-42
[c5]
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Cecilia De la Parra, Ahmed El-Yamany, Taha Soliman, Akash Kumar, Norbert Wehn, Andre Guntoro:
Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design. ISCAS 2021: 1-5
2020
[c4]
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Taha Soliman, Ricardo Olivo, Tobias Kirchner, Cecilia De la Parra, Maximilian Lederer, Thomas Kämpfe, Andre Guntoro, Norbert Wehn:
Efficient FeFET Crossbar Accelerator for Binary Neural Networks. ASAP 2020: 109-112
[c2]
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Taha Soliman, Ricardo Olivo, Tobias Kirchner, Maximilian Lederer, Thomas Kämpfe, Andre Guntoro, Norbert Wehn:
A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks. SoCC 2020: 96-101
2019
[c1]
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Matthias Jung, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn:
Fast validation of DRAM protocols with timed petri nets. MEMSYS 2019: 133-147

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