BibTeX record conf/aspdac/WangZCHHB08

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@inproceedings{DBLP:conf/aspdac/WangZCHHB08,
  author       = {Yanfeng Wang and
                  Qiang Zhou and
                  Yici Cai and
                  Jiang Hu and
                  Xianlong Hong and
                  Jinian Bian},
  editor       = {Chong{-}Min Kyung and
                  Kiyoung Choi and
                  Soonhoi Ha},
  title        = {Low power clock buffer planning methodology in {F-D} placement for
                  large scale circuit design},
  booktitle    = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
                  {ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
  pages        = {370--375},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ASPDAC.2008.4483977},
  doi          = {10.1109/ASPDAC.2008.4483977},
  timestamp    = {Thu, 20 Nov 2025 18:47:19 +0100},
  biburl       = {https://dblp.org/rec/conf/aspdac/WangZCHHB08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}