BibTeX record conf/cicc/SrinivasaBMCAH025

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@inproceedings{DBLP:conf/cicc/SrinivasaBMCAH025,
  author       = {Srivatsa Rangachar Srinivasa and
                  Prerna Budhkar and
                  Gauthaman Murali and
                  Vui Seng Chua and
                  Paolo A. Aseron and
                  Vinayak Honkote and
                  Ravi R. Iyer and
                  Nilesh Jain and
                  Dileep John Kurian and
                  Anuradha Srinivasan and
                  Tanay Karnik},
  title        = {A 68 TOPS/W, 256MB {SRAM} Sparse {GEMM} Accelerator Tiled Across 16,
                  4nm Near Memory Compute {(NMC)} Chiplets Disaggregated 2.5D System},
  booktitle    = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2025, Boston,
                  MA, USA, April 13-17, 2025},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2025},
  url          = {https://doi.org/10.1109/CICC63670.2025.10982895},
  doi          = {10.1109/CICC63670.2025.10982895},
  timestamp    = {Sun, 01 Jun 2025 22:06:11 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/SrinivasaBMCAH025.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}