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ORCID25th Hot Chips Symposium 2013: Stanford University, CA, USA
- 2013 IEEE Hot Chips 25 Symposium (HCS), Stanford University, CA, USA, August 25-27, 2013. IEEE 2013, ISBN 978-1-4673-8881-8
- John Sell, Patrick O'Connor:
Main SoC and XBOX one kinect. 1-18 - Ali Vahidsafa, Sutikshan Bhutani:
SPARC M6 Oracle's next generation processor for enterprise systems. 1-37 - Yunsup Lee, David Sheffield, Andrew Waterman, Michael J. Anderson, Kurt Keutzer, Krste Asanovic:
Measuring the gap between programmable and fixed-function accelerators: A case study on speech recognition. 1-2 - Jeff Stuecheli:
POWER8. 1-20 - Michaela Blott, Kees A. Vissers:
Dataflow architectures for 10Gbps line-rate key-value-stores. 1-25 - Amber Huffman:
Delivering the full potential of PCIe storage. 1-24 - Lucian Codrescu:
Qualcomm Hexagon DSP: An architecture optimized for mobile multimedia and communications. 1-23 - Robert J. Sonnelitter:
IBM zEC12 processor subsystem. 1-25 - Marco Ceriani, Simone Secchi, Antonino Tumeo
, Oreste Villa, Gianluca Palermo:
Exploring manycore multinode systems for irregular applications with FPGA prototyping. 1 - Maysam Lavasani, Hari Angepat, Derek Chiou:
An FPGA-based in-line accelerator for Memcached. 1-23 - Ehsan K. Ardestani, Gabriel Southern, Jason Doung, Elnaz Ebrahimi, Jose Renau:
ESESC: A fast performance, power, and temperature multicore simulator. 1 - Neil Vachharajani:
Flash in an enterprise storage array - 10x performance for less than disk. 1-10 - Dan Bouvier, Ben Bates, Walter Fry, Sreekanth Godey:
AMD "kabini" APU SOC. 1-25 - Ian Bratt:
HSA queueing. 1-43 - Kristopher Carver:
Microprocessors for roots-of-trust. 1-17 - Krste Asanovic, Jan-Willem van de Waerdt:
Welcome from general chairs. 1-2 - Toshio Yoshida:
SPARC64™ X+: Fujitsu's next generation processor for UNIX servers. 1-25 - Phil Rogers:
Heterogeneous system architecture overview. 1-41 - Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. 1 - Peter De Dobbelaere:
Silicon Photonics Technology Platform for integration of optical IOs with ASICs. 1-18 - Radoslav Danilak:
Design challenges in building an advanced NAND flash array controller for 19/20 nm MLC. 1-12 - Yoshio Masubuchi, Alan Jay Smith:
In memoriam. 1-2 - Gunnar Bublitz, Ralph Hasholzner, Christian Drewes:
Power management challenges in wireless WAN SoCs. 1-25 - Zoe Jeffrey, Xiaojun Zhai, Faycal Bensaali, Reza Sotudeh, Aladdin M. Ariyaeeinia:
Automatic number plate recognition system on an ARM-DSP and FPGA heterogeneous SoC platforms. 1-9 - David Flynn:
Flash adoption in the enterprise. 1-15 - Mieszko Lis, Keun Sup Shim, Brandon Cho, Ilia A. Lebedev, Srinivas Devadas:
Hardware-level thread migration in a 110-core shared-memory multiprocessor. 1-27 - Kevin Rowett:
Fast storage for big data - tutorial 2 implications of using flash devices in an enterprise storage server. 1-23 - Milton Ribeiro, John Carey:
5th generation touchscreen controller for mobile phones and tablets. 1-11 - Ari Studnitzer, Oskar Mencer:
Going to the wire: The next generation financial risk management platform. 1-26 - Praveen Dongara, Lloyd Bircher, John Darilek:
"Richland" client APU. 1-27 - David Kidd:
A 50% lower power ARM Cortex CPU using DDC technology with body bias. 1-21 - Per Hammarlund:
4th generation IntelTM Core processor, codenamed Haswell. 1-35 - Krishna Parat:
NAND technology. 1-18 - Thomas Wicki, Jurgen Schulz:
Bixby: The scalability and coherence directory ASIC in Oracle's highly scalable enterprise systems. 1-34 - Babak A. Parviz:
Being in the moment with Google glass. 1-22 - John D. Davis, Laura Caulfield, Steven Swanson:
Flash trends: Challenges and future. 1-42 - Marat Dukhan:
What a fast FPU means for algorithms: A story of vector elementary functions. 1 - Robert P. Colwell:
The chip design game at the end of Moore's law. 1-16 - Michael Brody:
The use and abuse of patents in the semiconductor industry. 1-79 - Michael J. Flynn, Donald K. Newell:
Welcome. 1-2 - Benedict R. Gaster:
HSA memory model. 1-42 - Ben Sander:
HSAIL: Portable compiler IR for HSA. 1-32 - Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David A. Patterson, Krste Asanovic:
The RISC-V instruction set. 1 - Gavin Stark, Sakir Sezer:
NFP-6xxx - a 22nm high-performance network flow processor for 200Gb/s Software Defined Networking. 1-21 - Mark Ewert, Prakash Iyer, Vandana Venkatesan:
Hotchips 2013: Clovertrail+ Smartphone SoC platform. 1-22 - Michael J. Miller:
Second generation bandwidth Engine® IC breaks 4.5 billion accesses/sec. 1-21
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