default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIntegration, Volume 8
Volume 8, Number 1, October 1989
- Lambert Spaanenburg:
Editorial. 1 - Marc Biver, Hubert Kaeslin, Carlo Tommasini:
Architectural design and realization of a single-chip Viterbi decoder. 3-16 - Kok-Phuang Tan, Tiow Seng Tan:
Switchbox routing using score function. 17-39 - Amnon Joseph, Ron Y. Pinter:
Feed-through river routing. 41-50 - A. Bouridane, A. Pajayakrit, Satnam Singh Dlay, A. G. J. Holt:
CMOS VLSI circuits of pipeline sections for 32 and 64-point Fermat number transformers. 51-64 - David J. Evans, Konstantinos G. Margaritis
:
Systolic block LU decompositions. 65-90
Volume 8, Number 2, November 1989
- Lambert Spannenburg:
Editorial. 97 - Bruno Rouzeyre, Toufic Ezzedine, Georges Sagnes:
Operators allocation in the silicon compiler SCOOP. 99-109 - Teofilo F. Gonzalez, Si-Qing Zheng:
Stretching and three-layer wiring planar layouts. 111-141 - Elena Lodi, Fabrizio Luccio, Linda Pagli:
Channel routing for strictly multiterminal nets. 143-153 - Peter D. Hortensius, Howard C. Card, Robert D. McLeod:
VLSI computing architectures for Ising model simulation. 155-172 - Luc J. M. Claesen, J. P. Schupp, P. Das, P. Johannes, S. Perremans, Hugo De Man:
Efficient false path elimination algorithms for timing verification by event graph preprocessing. 173-187 - Kenneth J. Schultz, David H. K. Hoe, C. André T. Salama:
A microprogrammable processor using single poly EPROM. 189-199
Volume 8, Number 3, December 1989
- Lambert Spaanenburg:
Editorial. 207 - Ganesh Gopalakrishnan, Richard M. Fujimoto, Venkatesh Akella, Narayana Mani:
HOP: A process model for synchronous hardware; semantics and experiments in process composition. 209-247 - Chidchanok Lursinsap, Daniel Gajski:
Power routing in channelless floorplan layouts. 249-268 - Fabrizio Lombardi:
On a new class of C-testable systolic arrays. 269-283 - Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap:
Bisection trees and half-quad trees: Memory and time efficient data structures for VLSI layout editors. 285-300 - Brian C. McKinney, Fayez El Guibaly:
VLSI design of an FFT processor network. 301-320 - G. E. A. Lousberg:
Two terminal channel routing using at most density plus two tracks. 321-330 - Chein-Wei Jen, Ding-Ming Kwai:
Multi-dimensional parallel computing structures for regular iterative algorithms. 331-340
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-16 00:14 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
