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ORCIDIEEE Transactions on Circuits and Systems II: Express Briefs, Volume 63
Volume 63-II, Number 1, January 2016
- Yichuang Sun, Baoyong Chi, Heng Zhang:
Guest Editorial for the Special Issue on Software-Defined Radio Transceivers and Circuits for 5G Wireless Communications. 1-3 - Rui Fiel Cordeiro, Arnaldo S. R. Oliveira
, José M. N. Vieira:
All-Digital Transmitter With a Mixed-Domain Combination Filter. 4-8 - Fikre Tsigabu Gebreyohannes, Antoine Frappé, Andreas Kaiser:
A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards. 9-13 - Souhir Lajnef, Noureddine Boulejfen, Abubakr Hassan Abdelhafiz, Fadhel M. Ghannouchi:
Two-Dimensional Cartesian Memory Polynomial Model for Nonlinearity and I/Q Imperfection Compensation in Concurrent Dual-Band Transmitters. 14-18 - Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Low-Complexity Pipelined Architecture for FBMC/OQAM Transmitter. 19-23 - Ross A. Elliot, Martin A. Enderwitz, Keith Thompson, Louise H. Crockett, Stephan Weiss, Robert W. Stewart:
Wideband TV White Space Transceiver Design and Implementation. 24-28 - Simran Singh, Mikko Valkama, Michael Epp, Wolfgang Schlecker:
Digitally Enhanced Wideband I/Q Downconversion Receiver With 2-Channel Time-Interleaved ADCs. 29-33 - Jose Augusto Lima, John W. M. Rogers, Rony E. Amaya:
Finding the Initial Estimate for the Diode Bias Point in Multiport Receivers. 34-38 - Alexander López-Parrado, Jaime Velasco-Medina:
Cooperative Wideband Spectrum Sensing Based on Sub-Nyquist Sparse Fast Fourier Transform. 39-43 - Xiaobao Yu, Meng Wei, Ying Song, Zhihua Wang, Baoyong Chi:
A PAPR-Aware Dual-Mode Subgigahertz CMOS Power Amplifier for Short-Range Wireless Communication. 44-48 - Haifeng Wu, Qian-Fu Cheng, Xu-Guang Li, Haipeng Fu:
Analysis and Design of an Ultrabroadband Stacked Power Amplifier in CMOS Technology. 49-53 - Tushar Sharma, Ramzi Darraji, Fadhel M. Ghannouchi:
A Methodology for Implementation of High-Efficiency Broadband Power Amplifiers With Second-Harmonic Manipulation. 54-58 - Abhishek Ambede, Shanker Shreejith, A. Prasad Vinod, Suhaib A. Fahmy:
Design and Realization of Variable Digital Filters for Software-Defined Radio Channelizers Using an Improved Coefficient Decimation Method. 59-63 - Alireza Mehrnia, Ming Dai, Alan N. Willson Jr.:
Efficient Halfband FIR Filter Structures for RF and IF Data Converters. 64-68 - Rakesh Gangarajaiah, Mohammed Abdulaziz, Henrik Sjöland, Peter Nilsson, Liang Liu:
A Digitally Assisted Nonlinearity Mitigation System for Tunable Channel Select Filters. 69-73 - Sameed Hameed, Mansour Rachid, Babak Daneshrad, Sudhakar Pamarti:
Frequency-Domain Analysis of N-Path Filters Using Conversion Matrices. 74-78 - Dimitra Psychogiou, Roberto Gómez-García, Dimitrios Peroulis:
High-Q Bandstop Filters Exploiting Acoustic-Wave-Lumped-Element Resonators (AWLRs). 79-83 - Mehmet Yuceer:
A Reconfigurable Microwave Combline Filter. 84-88 - Tayfun Nesimoglu, Cumali Sabah:
A Tunable Metamaterial Resonator Using Varactor Diodes to Facilitate the Design of Reconfigurable Microwave Circuits. 89-93 - Leo Laughlin, Chunqing Zhang, Mark A. Beach, Kevin A. Morris, John L. Haine:
Passive and Active Electrical Balance Duplexers. 94-98 - Han Le Duc, Duc Minh Nguyen, Chadi Jabbour, Tarik Graba, Patricia Desgreys, Olivier Jamin, Van Tam Nguyen:
All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition. 99-103 - Yoan Veyrac, Francois Rivet, Yann Deval, Dominique Dallet, Patrick Garrec, Richard Montigny:
A 65-nm CMOS DAC Based on a Differentiating Arbitrary Waveform Generator Architecture for 5G Handset Transmitter. 104-108 - Sujiang Rong, Jun Yin, Howard C. Luong:
A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13-µm CMOS Process. 109-113 - Muhammad Swilam, Mohamed El-Nozahi, Emad Hegazi:
Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter. 114-118
Volume 63-II, Number 2, February 2016
- Byoungho Kim:
Dithering Loopback-Based Prediction Technique for Mixed-Signal Embedded System Specifications. 121-125 - Liang-Jen Chen, Shen-Iuan Liu:
A 10-bit 40-MS/s Time-Domain Two-Step ADC With Short Calibration Time. 126-130 - Piotr Mitros:
Filters With Decreased Passband Error. 131-135 - Chi Deng, Yun Sheng, Shengyang Wang, Wei Hu, Shengxi Diao, Dahong Qian:
A CMOS Smart Temperature Sensor With Single-Point Calibration Method for Clinical Use. 136-140 - Ji-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae-Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. 141-145 - Yi-Hsiang Juan, Hong-Yi Huang, Shin-Chi Lai, Wen-Ho Juang, Shuenn-Yuh Lee, Ching-Hsing Luo:
A Distortion Cancelation Technique With the Recursive DFT Method for Successive Approximation Analog-to-Digital Converters. 146-150 - Hesham Omran, Rami T. ElAfandy, Muhammad Arsalan, Khaled N. Salama:
Direct Mismatch Characterization of Femtofarad Capacitors. 151-155 - Meilin Wan, Wang Liao, Kui Dai, Xuecheng Zou:
A Nonlinearity-Compensated All-MOS Voltage-to-Current Converter. 156-160 - Yingchieh Ho, Shu-Yu Hsu, Chen-Yi Lee:
A Variation-Tolerant Subthreshold to Superthreshold Level Shifter for Heterogeneous Interfaces. 161-165 - Wameedh Nazar Flayyih, Khairulmizam Samsudin, Shaiful Jahari Hashim, Yehea I. Ismail, Fakhrul Zaman Rokhani:
Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication. 166-170 - Pedro Reviriego, Mustafa Demirci, Adrian Evans, Juan Antonio Maestro:
A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits. 171-175 - Abdelkrim Kamel Oudjida, Ahmed Liacha, Mohammed Bakiri, Nicolas Chaillet:
Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design. 176-180 - Sumedh Dhabu, A. Prasad Vinod:
Design and FPGA Implementation of Reconfigurable Linear-Phase Digital Filter With Wide Cutoff Frequency Range and Narrow Transition Bandwidth. 181-185 - Mario Garrido, Petter Kallstrom, Martin Kumm, Oscar Gustafsson:
CORDIC II: A New Improved CORDIC Algorithm. 186-190 - Toshihiro Hori:
Relationship Between Smith Normal Form of Periodicity Matrices and Sampling of Two-Dimensional Discrete Frequency Distributions With Tiling Capability. 191-195 - Jia-Ching Wang, Chien-Yao Wang, Tzu-Chiang Tai, Min Shih, Shao-Chieh Huang, Ying-Chuan Chen, Yan-Yu Lin, Li-Xun Lian:
VLSI Design for Convolutive Blind Source Separation. 196-200 - Jun Fu, Tianyou Chai, Ying Jin, Chun-Yi Su:
Fault-Tolerant Control of a Class of Switched Nonlinear Systems With Structural Uncertainties. 201-205 - Yang Li, Xiaoqun Wu, Junan Lu, Jinhu Lu:
Synchronizability of Duplex Networks. 206-210 - Youngjoo Lee, Meng Li, Liesbet Van der Perre:
Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression. 211-215 - Pengda Huang:
A Novel Structure for Rayleigh Channel Generation With Consideration of the Implementation in FPGA. 216-220 - Kuntal Mandal, Soumitro Banerjee:
Synchronization Phenomena in Interconnected Power Electronic Systems. 221-225
Volume 63-II, Number 3, March 2016
- Gregor Tretter, David Fritsche, Mohammad Mahdi Khafaji, Corrado Carta, Frank Ellinger:
A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS. 229-233 - Mauro Santos, Nuno Horta, Jorge Guilherme:
Logarithmic AD Converter With Selectable Transfer Characteristic. 234-238 - Robert Tchitnga, Tekou Nguazon, Patrick H. Louodop Fotso, Jason Alfredo Carlson Gallas:
Chaos in a Single Op-Amp-Based Jerk Circuit: Experiments and Simulations. 239-243 - Dai Zhang, Atila Alvandpour:
A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS. 244-248 - Peyman Ahmadi, Brent Maundy, Ahmed S. Elwakil, Leonid Belostotski, Arjuna Madanayake:
A New Second-Order All-Pass Filter in 130-nm CMOS. 249-253 - Saroj Mondal, Roy P. Paily:
An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer. 254-258 - Hyoungho Ko, Takhyung Lee, Jihoon Kim, Jong-ae Park, Jongpal Kim:
Ultralow-Power Bioimpedance IC With Intermediate Frequency Shifting Chopper. 259-263 - Sang-Hye Chung, Young-Ju Kim, Yong-Hun Kim, Lee-Sup Kim:
A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS. 264-268 - Hoyoung Yoo, Youngjoo Lee, In-Cheol Park:
Low-Power Parallel Chien Search Architecture Using a Two-Step Approach. 269-273 - Mengdi Jiang, Wei Liu, Yi Li:
Adaptive Beamforming for Vector-Sensor Arrays Based on a Reweighted Zero-Attracting Quaternion-Valued LMS Algorithm. 274-278 - Shin-Chi Lai, Wen-Ho Juang, Yueh-Shu Lee, Shin-Hao Chen, Ke-Horng Chen, Chia-Chun Tsai, Chiung-Hon Lee:
Hybrid Architecture Design for Calculating Variable-Length Fourier Transform. 279-283 - Ljubisa Stankovic:
On the STFT Inversion Redundancy. 284-288 - Ju-Hong Lee, Jiun-Shian Du:
Phase Characteristics for the Stability of 2-D Quarter-Plane Recursive Digital All-Pass Filters. 289-293 - Sergio F. Almeida, José Mireles, Ernest J. Garcia, David Zubia:
MEMS Closed-Loop Control Incorporating a Memristor as Feedback Sensing Element. 294-298 - Shaolin Tan, Yaonan Wang, Yao Chen:
A Unified Tractable Approach for Random Drifts on Dynamical Networks. 299-303 - Guanghui Wen, Michael Z. Q. Chen, Xinghuo Yu:
Event-Triggered Master-Slave Synchronization With Sampled-Data Communication. 304-308 - Fangfei Li:
Pinning Control Design for the Synchronization of Two Coupled Boolean Networks. 309-313 - Yuanshi Zheng, Long Wang:
Consensus of Switched Multiagent Systems. 314-318
Volume 63-II, Number 4, April 2016
- Alireza Bafandeh, Mohammad Yavari:
Digital Calibration of Amplifier Finite DC Gain and Gain Bandwidth in MASH ΣΔ Modulators. 321-325 - Mina Kim, Christopher M. Twigg:
Rank Determination by Winner-Take-All Circuit for Rank Modulation Memory. 326-330 - Xiaochen Yang, Guoping Cui, Yang Zhang, Jiajun Ren, Jin Liu:
A Metastability Error Detection and Reduction Technique for Partially Active Flash ADCs. 331-335 - Yufeng Xie, Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Qingtian Zou, Ryan Huang, Jingang Wu:
A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. 336-340 - Junfeng Gao, Guangjun Li, Letian Huang, Qiang Li:
An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency. 341-345 - Liang Wen, Xu Cheng, Shudong Tian, Haibo Wen, Xiaoyang Zeng:
Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error. 346-350 - Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
A 2-µW 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop. 351-355 - Inyong Kwon, Taehoon Kang, Byron T. Wells, Lawrence D'Aries, Mark D. Hammig:
A High-Gain 1.75-GHz Dual-Inductor Transimpedance Amplifier With Gate Noise Suppression for Fast Radiation Detection. 356-360 - Sunsik Woo, Je-Kwang Cho:
A Switched-Capacitor Filter With Reduced Sensitivity to Reference Noise for Audio-Band Sigma-Delta D/A Converters. 361-365 - Dariusz Koscielnik, Dominik Rzepka, Jakub Szyduczynski:
Sample-and-Hold Asynchronous Sigma-Delta Time Encoding Machine. 366-370 - Ilseop Lee, Byoungho Kim, Byung-Geun Lee:
A Low-Power Incremental Delta-Sigma ADC for CMOS Image Sensors. 371-375 - Bartosz Boguslawski, Frédéric Heitzmann, Benoit Larras, Fabrice Seguin:
Energy-Efficient Associative Memory Based on Neural Cliques. 376-380 - Weijun Li, Feng Yu, Zhen-guo Ma:
Efficient Circuit for Parallel Bit Reversal. 381-385 - Choon Ki Ahn, Peng Shi:
Generalized Dissipativity Analysis of Digital Filters With Finite-Wordlength Arithmetic. 386-390 - Tao Yang, Ziyang Meng, Wei Ren, Karl Henrik Johansson:
Synchronization of Coupled Nonlinear Dynamical Systems: Interplay Between Times of Connectivity and Integral of Lipschitz Gain. 391-395 - Arturo Buscarino, Claudia Corradino, Luigi Fortuna, Mattia Frasca, Julien Clinton Sprott:
Nonideal Behavior of Analog Multipliers for Chaos Generation. 396-400 - Huaqing Li, Guo Chen, Xiaofeng Liao, Tingwen Huang:
Leader-Following Consensus of Discrete-Time Multiagent Systems With Encoding-Decoding. 401-405 - Zhiqiang Zhang, Lin Zhang, Fei Hao, Long Wang:
Periodic Event-Triggered Consensus With Quantization. 406-410
Volume 63-II, Number 5, May 2016
- Somnath Kundu, Chris H. Kim:
A 0.0054-mm2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor. 413-417 - Roger Yubtzuan Chen, Zong-Yi Yang:
CMOS Transimpedance Amplifier for Gigabit-per-Second Optical Wireless Communications. 418-422 - Jinxiang Zha, He Huang, Yujie Liu:
A Novel Window Function for Memristor Model With Application in Programming Analog Circuits. 423-427 - Joseph Shor, Dror Zilberman:
An Accurate Bandgap-Based Power-on-Detector in 14-nm CMOS Technology. 428-432 - Mohamed Amin, Bosco Leung:
Design Techniques for Linearity in Time-Based ΣΔ Analog-to-Digital Converter. 433-437 - Weize Yu, Selçuk Köse:
Charge-Withheld Converter-Reshuffling: A Countermeasure Against Power Analysis Attacks. 438-442 - K. S. Rakshitdatta, Yujendra Mitikiri, Nagendra Krishnapura:
A 12.5 mW, 11.1 nV√Hz, -115 dB THD, Settling, 18 bit SAR ADC Driver in 0.6 µm CMOS. 443-447 - Yi-Lin Tsai, Chun-Yu Lin, Bang-Cyuan Wang, Tsung-Hsien Lin:
A 330-µW 400-MHz BPSK Transmitter in 0.18- µm CMOS for Biomedical Applications. 448-452 - Jeffrey Prinzie, Michiel Steyaert, Paul Leroux:
A Self-Calibrated Bang-Bang Phase Detector for Low-Offset Time Signal Processing. 453-457 - Vincenzo Fiore, Egidio Ragonese, Giuseppe Palmisano:
Low-Power ASK Detector for Low Modulation Indexes and Rail-to-Rail Input Range. 458-462 - Mohsen Hayati, Moslem Nouri, Derek Abbott, Saeed Haghiri:
Digital Multiplierless Realization of Two-Coupled Biological Hindmarsh-Rose Neuron Model. 463-467 - Lokesh Garg, Vineet Sahula:
Macromodels for Static Virtual Ground Voltage Estimation in Power-Gated Circuits. 468-472 - Guo-Qing Lei, Yong Dou, Rongchun Li, Fei Xia:
An FPGA Implementation for Solving the Large Single-Source-Shortest-Path Problem. 473-477 - Eesa Nikahd, Payman Behnam, Reza Sameni:
High-Speed Hardware Implementation of Fixed and Runtime Variable Window Length 1-D Median Filters. 478-482 - Jea Hack Lee, Myung Hoon Sunwoo:
Low-Complexity First-Two-Minimum-Values Generator for Bit-Serial LDPC Decoding. 483-487 - Jorge Fernández-Berni, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez:
Single-Exposure HDR Technique Based on Tunable Balance Between Local and Global Adaptation. 488-492 - Fuyi Huang, Jiashu Zhang, Sheng Zhang:
Combined-Step-Size Affine Projection Sign Algorithm for Robust Adaptive Filtering in Impulsive Interference Environments. 493-497 - Kun-Zhi Liu, Rui Wang, Guo-Ping Liu:
Tradeoffs Between Transmission Intervals and Delays for Decentralized Networked Control Systems Based on a Gain Assignment Approach. 498-502 - Jia Mao, Zhuo Zou, Li-Rong Zheng:
A UWB-Based Sensor-to-Time Transmitter for RF-Powered Sensing Applications. 503-507 - Ying-Khai Teh, Philip K. T. Mok:
DTMOS-Based Pulse Transformer Boost Converter With Complementary Charge Pump for Multisource Energy Harvesting. 508-512
Volume 63-II, Number 6, June 2016
- Sevil Zeynep Lulec, David A. Johns, Antonio Liscidini:
A Simplified Model for Passive-Switched-Capacitor Filters With Complex Poles. 513-517 - Hyun-Wook Kang, Hyeok-Ki Hong, Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn, Seung-Tak Ryu:
A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs. 518-522 - Zhangming Zhu, Wenbin Bai:
A 0.5-V 1.3-µW Analog Front-End CMOS Circuit. 523-527 - Stefano Brenna, Fabio Padovan, Andrea Neviani, Andrea Bevilacqua, Andrea Bonfanti, Andrea L. Lacaita:
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS. 528-532 - Kihyun Kim, Jaeyong Ko, Sungho Lee, Sangwook Nam:
A Two-Stage Broadband Fully Integrated CMOS Linear Power Amplifier for LTE Applications. 533-537 - Federico Pepe, Pietro Andreani:
Still More on the 1/f2 Phase Noise Performance of Harmonic Oscillators. 538-542 - Ananiah Durai Sundararajan, S. M. Rezaul Hasan:
Quadruply Split Cross-Driven Doubly Recycled gm-Doubling Recycled Folded Cascode for Microsensor Instrumentation Amplifiers. 543-547 - Sung-Geun Kim, Jinsoo Rhim, Dae Hyun Kwon, Min-Hyeong Kim, Woo-Young Choi:
A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO. 548-552 - Hyunjoong Lee, Daeyong Shim, Cyuyeol Rhee, Mino Kim, Suhwan Kim:
A Sub-1.0-V On-Chip CMOS Thermometer With a Folded Temperature Sensor for Low-Power Mobile DRAM. 553-557 - Yuriy V. Pershin, Leonardo K. Castelano, Fabian Hartmann, Victor Lopez-Richard, Massimiliano Di Ventra:
A Memristive Pascaline. 558-562 - Shuanghe Yu, Xiaojun Long:
Finite-Time Consensus Tracking of Perturbed High-Order Agents With Relative Information by Integral Sliding Mode. 563-567 - Shiann-Rong Kuang, Chih-Yuan Liang, Chun-Chi Chen:
An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication. 568-572 - Kang-Sub Kwak, Jong-Hyun Ra, Ho-Sung Moon, Seong-Kwan Hong, Oh-Kyong Kwon:
A Low-Power Two-Tap Voltage-Mode Transmitter With Precisely Matched Output Impedance Using an Embedded Calibration Circuit. 573-577 - Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM. 578-582 - Nicholai L'Esperance, Timothy Platt, Mustapha Slamani, Tian Xia:
OFDM Multitone Signal Generation Technique for Analog Circuitry Test Characterization. 583-587 - Lu Lu, Haiquan Zhao, Badong Chen:
Improved-Variable-Forgetting-Factor Recursive Algorithm Based on the Logarithmic Cost for Volterra System Identification. 588-592 - Gabriel Caffarena, Daniel Ménard:
Quantization Noise Power Estimation for Floating-Point DSP Circuits. 593-597 - Enjin Fu, Pengfei Wu, Z. Rena Huang, Valencia Joyner Koomson:
Monolithic Low-Power 6-Gb/s Optical Transmitter for a Silicon HBT-Based Carrier Injection Electroabsorption Modulator. 598-602 - Kanata Isobe, Hiroyuki Torikai:
A Novel Hardware-Efficient Asynchronous Cellular Automaton Model of Spike-Timing-Dependent Synaptic Plasticity. 603-607 - Dongsheng Liu, Zilong Liu, Lun Li, Xuecheng Zou:
A Low-Cost Low-Power Ring Oscillator-Based Truly Random Number Generator for Encryption on Smart Cards. 608-612
Volume 63-II, Number 7, July 2016
- Ze-kun Zhou, Yue Shi, Chao Gou, Xia Wang, Gang Wu, Jie-fei Feng, Zhuo Wang, Bo Zhang:
A Resistorless Low-Power Voltage Reference. 613-617 - Joonhoi Hur, Hyoungsoo Kim, Ockgoo Lee, Kwan-Woo Kim, Franklin Bien, Kyutae Lim, Chang-Ho Lee, Joy Laskar:
A Multilevel Class-D CMOS Power Amplifier for an Out-Phasing Transmitter With a Nonisolated Power Combiner. 618-622 - Peng Wang, Trond Ytterdal:
A 54-µW Inverter-Based Low-Noise Single-Ended to Differential VGA for Second Harmonic Ultrasound Probes in 65-nm CMOS. 623-627 - Bibhudatta Sahoo, Amol Inamdar:
Thermal-Noise-Canceling Switched-Capacitor Circuit. 628-632 - Chih-Lu Wei, Shen-Iuan Liu:
A Digital PLL Using Oversampling Delta-Sigma TDC. 633-637 - Yongkui Yang, Jun Zhou, Xin Liu, Jia Hao Cheong, Wang Ling Goh:
A 151-nW Adaptive Delta-Sampling ADC for Ultra-Low Power Sensing Applications. 638-642 - Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, Xiaoyang Zeng:
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. 643-647 - Georges Kaddoum, Ebrahim A. Soujeri:
NR-DCSK: A Noise Reduction Differential Chaos Shift Keying System. 648-652 - Marco De Piante, Andrea M. Tonello:
On Impedance Matching in a Power-Line-Communication System. 653-657 - Apsara Ravish Suvarna, Venumadhav Bhagavatula, Jacques Christophe Rudell:
Transformer-Based Tunable Matching Network Design Techniques in 40-nm CMOS. 658-662 - Tao Yang, Ziyang Meng, Dimos V. Dimarogonas, Karl Henrik Johansson:
Periodic Behaviors for Discrete-Time Second-Order Multiagent Systems With Input Saturation Constraints. 663-667 - Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei:
A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation. 668-672 - Byeong Yong Kong, Hoyoung Yoo, In-Cheol Park:
Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes. 673-677 - Ramtin Zand, Arman Roohi, Soheil Salehi, Ronald F. DeMara:
Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design. 678-682 - Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation. 683-687 - Dawei Liu, Simon J. Hollis, Harry C. P. Dymond, Neville McNeill, Bernard H. Stark:
Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance. 688-692 - Wen Sun, Jinhu Lu, Xinghuo Yu, Yao Chen, Shihua Chen:
Cooperation of Multiagent Systems With Mismatch Parameters: A Viewpoint of Power Systems. 693-697 - Michele Bonnin, Fabio L. Traversa, Fabrizio Bonani:
Influence of Amplitude Fluctuations on the Noise-Induced Frequency Shift of Noisy Oscillators. 698-702 - Aimin Jiang, Hon Keung Kwan, Yanping Zhu, Ning Xu, Xiaofeng Liu:
Efficient WLS Design of IIR Digital Filters Using Partial Second-Order Factorization. 703-707 - Mohammad Sadegh Alizadeh, Javad Bagherzadeh, Mohammad Sharifkhani:
A Low-Latency QRD-RLS Architecture for High-Throughput Adaptive Applications. 708-712
Volume 63-II, Number 8, August 2016
- Ahmed I. Hussein, Ahmed Nader Mohieldin, Faisal Hussien, Ahmed Eladawy:
A Low-Distortion High-Efficiency Class-D Audio Amplifier Based on Sliding Mode Control. 713-717 - Guoyong Shi:
On the Nonconvergence of the Vector Fitting Algorithm. 718-722 - Shailesh Singh Chouhan, Kari Halonen:
A 0.67-µW 177-ppm/°C All-MOS Current Reference Circuit in a 0.18-µm CMOS Technology. 723-727 - Negar Reiskarimian, Jin Zhou, Tsung-Hao Chuang, Harish Krishnaswamy:
Analysis and Design of Two-Port N-Path Bandpass Filters With Embedded Phase Shifting. 728-732 - Dongil Lee, Taeho Lee, Young-Ju Kim, Lee-Sup Kim:
A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector. 733-737 - Blaise Ravelo:
Innovative Theory on Multiband NGD Topology Based on Feedback-Loop Power Combiner. 738-742 - Prakash Harikumar, J. Jacob Wikner, Atila Alvandpour:
A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications. 743-747 - Riccardo Trinchero, Paolo Manfredi, Igor S. Stievano, Flavio G. Canavero:
Steady-State Analysis of Switching Converters via Frequency-Domain Circuit Equivalents. 748-752 - Bodapati Srinivasu, K. Sridharan:
Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology. 753-757 - Leonardo Vera, John R. Long:
A 40-Gb/s 211-1 PRBS With Distributed Clocking and a Trigger Countdown Output. 758-762 - Amirreza Yousefzadeh, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco:
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links. 763-767 - Mahendra Sakare, Sadhu Pavan Kumar, Shalabh Gupta:
Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits. 768-772 - Guanzhong Huang, Chao Yu, Anding Zhu:
Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCs. 773-777 - Daisaburo Yoshioka, Kento Kawano:
Periodic Properties of Chebyshev Polynomial Sequences Over the Residue Ring ℤ/2kℤ. 778-782 - Xiaoming Chen, Boxun Li, Yu Wang, Yongpan Liu, Huazhong Yang:
A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution. 783-787 - Zongyu Zuo, Zongli Lin, Zhengtao Ding:
Truncated Prediction Output Feedback Control of a Class of Lipschitz Nonlinear Systems With Input Delay. 788-792 - Xi Zhu, Guanghui He:
An Area Time-Efficient Structure to Find the Approximate First Two Minima for Min-Sum-Based LDPC Decoders. 793-797 - Sung Hyun You, Jung-Min Pak, Choon Ki Ahn, Peng Shi, Myo-Taeg Lim:
Unbiased Finite-Memory Digital Phase-Locked Loop. 798-802 - Xiaobo Yin, Feng Yu, Zhen-guo Ma:
Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths. 803-807 - Luigi Alfredo Grieco, Mahdi Ben Alaya, Thierry Monteil, Khalil Drira:
Diameter-Constrained Overlays With Faulty Links: Equilibrium, Stability, and Upper Bounds. 808-812
Volume 63-II, Number 9, September 2016
- Chin-Yu Lin, Chien-Heng Wong, Chia-Hau Hsu, Yen-Hsin Wei, Tai-Cheng Lee:
A 200-MS/s Phase-Detector-Based Comparator With 400-μVrms Noise. 813-817 - H. Taghavi, Mohammadhassan Akbarpour, Fadhel M. Ghannouchi:
Sequential Load-Pull Technique for Multioctave Design of RF Power Amplifiers. 818-822 - Haiwei Zhang, Quan Xue:
60-GHz CMOS Current-Combining PA With Adaptive Back-Off PAE Enhancement. 823-827 - Jun Peng, Songbai He, Bingwen Wang, Zhijiang Dai, Jingzhou Pang:
Digital Predistortion for Power Amplifier Based on Sparse Bayesian Learning. 828-832 - Gustavo C. Martins, Wouter A. Serdijn:
Multistage Complex-Impedance Matching Network Analysis and Optimization. 833-837 - Fei Cheng, Wenwu Yu, Ying Wan, Jinde Cao:
Distributed Robust Control for Linear Multiagent Systems With Intermittent Communications. 838-842 - Zhao Wang, Jian Sun, Jie Chen:
A New Polytopic Approximation Method for Networked Systems With Time-Varying Delay. 843-847 - Mengyao Zhu, Yajun Ha, Chengcun Gu, Liuchuang Gao:
An Optimized Logarithmic Converter With Equal Distribution of Relative Errors. 848-852 - Chun-Hsien Yeh, Pei-Yin Chen, Yen-Chen Lai, Hao-Ting Lin, Chia-Hao Li, Pei-Hua Chang:
Real-Time Digital Hardware Simulation of the Rodless Pneumatic System. 853-857 - Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel:
A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. 858-862 - Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm. 863-867 - Mario Garrido:
The Feedforward Short-Time Fourier Transform. 868-872 - Di Wu, Yun Chen, Qichen Zhang, Yeong-Luh Ueng, Xiaoyang Zeng:
Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders. 873-877 - Viet-Thanh Pham, Sajad Jafari, Christos K. Volos, Aggelos Giakoumis, Sundarapandian Vaidyanathan, Tomasz Kapitaniak:
A Chaotic System With Equilibria Located on the Rounded Square Loop and Its Circuit Implementation. 878-882 - Victor Hugo Pereira Rodrigues, Tiago Roux Oliveira, José Paulo V. S. Cunha:
Globally Stable Synchronization of Chaotic Systems Based on Norm Observers Connected in Cascade. 883-887 - Won-Jin Lee, Seong-Won Lee:
Improved Spatiotemporal Noise Reduction for Very Low-Light Environments. 888-892 - Choon Ki Ahn, Peng Shi, Hamid Reza Karimi:
Novel Results on Generalized Dissipativity of Two-Dimensional Digital Filters. 893-897 - Chong-Yi Liou, Chi-Jung Kuo, Shau-Gang Mao:
Wireless-Power-Transfer System Using Near-Field Capacitively Coupled Resonators. 898-902 - Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Wing-Hung Ki:
Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators. 903-907
Volume 63-II, Number 10, October 2016
- Karim O. Ragab, Hassan Mostafa, Ahmed Eladawy:
A Novel 10-Bit 2.8-mW TDC Design Using SAR With Continuous Disassembly Algorithm. 909-913 - J. Elkind, Eran Socher:
Noise Figure Optimization Tool for Millimeter-Wave Receivers at Near-fmax Frequencies. 914-918 - Amir Hossein Rasekh, Mehrdad Sharif Bakhtiar:
Compensation Method for Multistage Opamps With High Capacitive Load Using Negative Capacitance. 919-923 - Yulin Zhang, Edoardo Bonizzoni, Franco Maloberti:
A 10-b 200-kS/s 250-nA Self-Clocked Coarse-Fine SAR ADC. 924-928 - Pietro Ciccarella, Marco Carminati, Giorgio Ferrari, Davide Bianchi, Stefano Grillanda, Francesco Morichetti, Andrea Melloni, Marco Sampietro:
Impedance-Sensing CMOS Chip for Noninvasive Light Detection in Integrated Photonics. 929-933 - Boyu Hu, Fengbo Ren, Zuow-Zun Chen, Xicheng Jiang, Mau-Chung Frank Chang:
An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search. 934-938 - Arthur Spivak, Alexander Belenky, Orly Yadid-Pecht:
Very Sensitive Low-Noise Active-Reset CMOS Image Sensor With In-Pixel ADC. 939-943 - Behnam Kia, John F. Lindner, William L. Ditto:
A Simple Nonlinear Circuit Contains an Infinite Number of Functions. 944-948 - Yinman Lee:
Low-Complexity MIMO Detection: A Mixture of Basic Techniques for Near-Optimal Error Rate. 949-953 - Gwang-Ho Lee, Tae-Hwan Kim:
Implementation of a Near-Optimal Detector for Spatial Modulation MIMO Systems. 954-958 - Quoc-Viet Pham, Won-Joo Hwang:
Resource Allocation for Heterogeneous Traffic in Complex Communication Networks. 959-963 - Ki-Ryong Kim, Hanwool Jeong, Juhyun Park, Seong-Ook Jung:
Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution. 964-968 - Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. 969-973 - Mario Garrido, Shen-Jui Huang, Sau-Gee Chen, Oscar Gustafsson:
The Serial Commutator FFT. 974-978 - Zhao-Bin Ma, Yang Yang, Yun-Xia Liu, Anil Anthony Bharath:
Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing. 979-983 - Jun Han, Yicheng Zhang, Shan Huang, Mengyuan Chen, Xiaoyang Zeng:
An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor. 984-988 - Mariane R. Petraglia, Diego B. Haddad, Elias L. Marques:
Affine Projection Subband Adaptive Filter With Low Computational Complexity. 989-993 - Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh:
UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications. 994-998 - Chunxiao Fan, Yi Niu, Guangming Shi, Fu Li, Fei Qi, Xuemei Xie, Dandan Jiao:
An Improved Signed Digit Representation Approach for Constant Vector Multiplication. 999-1003 - Mohamed Darwish, Mohamed Mohsen, Ahmed Saad, Jeffrey A. Weldon:
Ultralow-Area Hysteretic Control LDO With Sub-1-µA Quiescent Current. 1004-1008
Volume 63-II, Number 11, November 2016
- Zhigang Qin, Akihiro Tanaka, Naomi Takaya, Hirokazu Yoshizawa:
0.5-V 70-nW Rail-to-Rail Operational Amplifier Using a Cross-Coupled Output Stage. 1009-1013 - Hyun-A. Ahn, Seong-Kwan Hong, Oh-Kyong Kwon:
A Fast Switching Current Regulator Using Slewing Time Reduction Method for High Dimming Ratio of LED Backlight Drivers. 1014-1018 - Ping Lu, Ying Wu, Pietro Andreani:
A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration. 1019-1023 - Taehwan Joo, Dong-Ho Lee, Songcheol Hong:
A Fully Integrated RF CMOS Front-End IC for Connectivity Applications. 1024-1028 - Christian Venerus, Jason Remple, Ian Galton:
Simplified Logic for Tree-Structure Segmented DEM Encoders. 1029-1033 - Yoonsoo Kim, Gyu-Seob Jeong, Jun-Eun Park, Joonbae Park, Gyungock Kim, Deog-Kyoon Jeong:
20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS. 1034-1038 - Ritesh Bhat, Harish Krishnaswamy:
Design Tradeoffs and Predistortion of Digital Cartesian RF-Power-DAC Transmitters. 1039-1043 - Archit Joshi, Gagan Midha:
Bandwidth Compensation Technique for Digital PLL. 1044-1048 - Yousof Mortazavi, Wooyoung Jung, Brian L. Evans, Arjang Hassibi:
A Mostly Digital PWM-Based ΔΣ ADC With an Inherently Matched Multibit Quantizer/DAC. 1049-1053 - Tianyu Zhang, Wenquan Che:
A Compact Tunable Power Divider With Wide Tuning Frequency Range and Good Reconfigurable Responses. 1054-1058 - Hanwool Jeong, Juhyun Park, Tae Woo Oh, Woojin Rim, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. 1059-1063 - Yiran Xu, Jian Hu, Jun Xiao, Guangjun Yang, Weiran Kong:
Design Techniques for a 30-ns Access Time 1.5-V 200-KB Embedded EEPROM Memory. 1064-1068 - Shady O. Agwa, Eslam Yahya, Yehea Ismail:
ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing. 1069-1073 - Jiankun Sun, Jun Yang, Wei Xing Zheng, Shihua Li:
GPIO-Based Robust Control of Nonlinear Uncertain Systems Under Time-Varying Disturbance With Application to DC-DC Converter. 1074-1078 - Bijit Kumar Das, Mrityunjoy Chakraborty, Jerónimo Arenas-García:
Sparse Distributed Estimation via Heterogeneous Diffusion Adaptive Networks. 1079-1083 - Peter Jingjing Xia, Eric Ng, Slim Boumaiza:
Wideband Compensation of RF Vector Multiplier for RF Predistortion Systems. 1084-1088
Volume 63-II, Number 12, December 2016
- Alyssa B. Apsel, Chai Wah Wu, Eduard Alarcón:
Guest Editorial. 1089-1090 - Alon Ascoli, Ronald Tetzlaff, Leon O. Chua:
The First Ever Real Bistable Memristors - Part I: Theoretical Insights on Local Fading Memory. 1091-1095 - Alon Ascoli, Ronald Tetzlaff, Leon O. Chua:
The First Ever Real Bistable Memristors - Part II: Design and Analysis of a Local Fading Memory System. 1096-1100 - Dongsheng Yu, Zhi Zhou, Herbert Ho-Ching Iu, Tyrone Fernando, Yihua Hu:
A Coupled Memcapacitor Emulator-Based Relaxation Oscillator. 1101-1105 - Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS. 1106-1110 - Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. 1111-1115 - Marcello De Matteis, Federica Resta, Alessandra Pipino, Stefano D'Amico, Andrea Baschirotto:
A 28.8-MHz 23-dBm-IIP3 3.2-mW Sallen-Key Fourth-Order Filter With Out-of-Band Zeros Cancellation. 1116-1120 - Vamsi Talla, Joshua R. Smith:
Design and Analysis of a High Bandwidth Rectifying Regulator With PWM and PFM Modes. 1121-1125 - Gain Kim, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces. 1126-1130 - Bo Yuan, Yanzhi Wang, Zhongfeng Wang:
Area-Efficient Scaling-Free DFT/FFT Design Using Stochastic Computing. 1131-1135 - Yuming Zhuang, Degang Chen:
New Strategies in Removing Noncoherency From Signals With Large Distortion-to-Noise Ratios. 1136-1140 - Mohammad Najjarzadegan, Ghasem Pasandi, Sied Mehdi Fakhraie:
A Novel Integer-Bit Estimation Scheme in Digital Filters Based on Probabilistic Behavior of Signals in the Internal Nodes. 1141-1145 - Jinho Han, Youngsu Kwon, Kyeongjin Byun, Hoi-Jun Yoo:
A Fault-Tolerant Cache System of Automotive Vision Processor Complying With ISO26262. 1146-1150 - Chacko John Deepu, Xiaoyang Zhang, Chun-Huat Heng, Yong Lian:
A 3-Lead ECG-on-Chip with QRS Detection and Lossless Compression for Wireless Sensors. 1151-1155 - Michael A. Suster, Nicholas H. Vitale, Debnath Maji, Pedram Mohseni:
A Circuit Model of Human Whole Blood in a Microfluidic Dielectric Sensor. 1156-1160 - Siddharth Joshi, Chul Kim, Gert Cauwenberghs:
A 6.5-µW/MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing. 1161-1165 - Yao-Sheng Hu, Po-Chao Huang, Hung-Yen Tai, Hsin-Shu Chen:
A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC. 1166-1170 - Sung-En Hsieh, Chih-Cheng Hsieh:
A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS. 1171-1175
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