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ORCIDVLSI Design, Volume 11
Volume 11, Number 1, 2000
- Parag K. Lala:
Guest Editorial. - Alexej Dmitriev, Valerij V. Saposhnikov, Vladimir V. Saposhnikov, Michael Gössel, V. Moshanin, Andrej A. Morosov:
New Self-dual Circuits for Error Detection and Testing. 1-21 - Cecilia Metra, Michele Favalli, Bruno Riccò:
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits. 23-34 - Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos:
Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes. 35-45 - Anzhela Yu. Matrosova, Ilya Levin
, Sergey Ostanin:
Self-checking Synchronous FSM Network Design with Low Overhead. 47-58 - Emmanuel Simeu:
Optimal Detector Design for On-line Testing of Linear Analog Systems. 59-74
Volume 11, Number 2, 2000
- L. M. Patnaik, Satrajit Gupta:
Exact Output Response Computation of RC Interconnects Under General Polynomial Input Waveforms. 75-84 - Bogdan J. Falkowski, Radomir S. Stankovic:
Spectral Interpretation and Applications of Decision Diagrams. 85-105 - Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop. 107-113 - Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. 115-128 - Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda:
νMOS-based Sorter for Arithmetic Applications. 129-136 - Yanjun Zhang, Si-Qing Zheng:
An Efficient Parallel VLSI Sorting Architecture. 137-147 - Chien-In Henry Chen, Yingjie Zhou:
Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs. 149-159 - Dong-Wook Kim, Tae-Yong Choi:
Delay Time Estimation Model for Large Digital CMOS Circuits. 161-173
Volume 11, Number 3, 2000
- Youssef Saab:
Guest Editorial. - Sao-Jie Chen, Chung-Kuan Cheng:
Tutorial on VLSI Partitioning. 175-218 - Huiqun Liu, Kai Zhu, D. F. Wong:
FPGA Partitioning with Complex Resource Constraints. 219-235 - Roman P. Bazylevych, R. A. Melnyk, O. G. Rybak:
Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method. 237-248 - Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Iterative Partitioning with Varying Node Weights. 249-258 - Shawki Areibi, Anthony Vannelli:
Tabu Search: A Meta Heuristic for Netlist Partitioning. 259-283 - George Karypis, Vipin Kumar:
Multilevel k-way Hypergraph Partitioning. 285-300 - Youssef Saab:
A New 2-way Multi-level Partitioning Algorithm. 301-310
Volume 11, Number 4, 2000
- Bogdan J. Falkowski, Chip-Hong Chang:
Minimization of k-Variable-Mixed-Polarity Reed-Muller Expansions. 311-320 - Antonio J. López-Martín, Alfonso Carlosena:
Design of MOS-translinear Multiplier/Dividers in Analog VLSI. 321-329 - Chua-Chin Wang, Chenn-Jung Huang, I-Yen Chang:
Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library. 331-338 - D. Torres Roman, J. Gonzalez, M. Guzman:
A New Bus Assignment Algorithm for a Shared Bus Switch Fabric. 339-351 - Chua-Chin Wang, Chenn-Jung Huang, Po-Ming Lee:
Design and Analysis of Digital Ratioed Compressors for Inner Product Processing. 353-361 - Andrew G. Dempster:
Graphical Design Techniques for Fixed-point Multiplication. 363-379 - Chaeryung Park, Taewhan Kim, C. L. Liu:
An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. 381-396 - S. Masupe, Tughrul Arslan:
Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors. 397-403 - D. Torres Roman, A. Larios, M. Guzman:
A Chip for a Routing Table Based on a Novel Modified Trie Algorithm. 405-415
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