default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVLSI Design, Volume 2
Volume 2, Number 1, 1994
- Peter J. Ashenden, Henry Detmold, Wayne S. McKeen:
Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms. 1-16 - Nohbyung Park, Fadi J. Kurdahi
:
Register-Transfer Synthesis of Pipelined Data Paths. 17-32 - Andrzej Sobski, Alexander Albicki:
High Throughput Error Control Using Parallel CRC. 33-50 - Spyros Tragoudas:
On Channel Routing Problems With Interchangeable Terminals. 51-68 - Anand V. Hudli, Raghu V. Hudli:
Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits. 69-80 - Rafic Z. Makki, Shyang-Tai Su:
Analysis and Characterization of State Assignment Techniques for Sequential Machines. 81-88
Volume 2, Number 2, 1994
- Si-Qing Zheng, Dian Zhou:
Preface. i - Kuo-Hua Wang, Cheng Chen, Ting Ting Hwang:
Technology Mapping for FPGA Using Generalized Functional Decomposition. 89-103 - Subbu Muddappa, Rafic Z. Makki, Zbigniew Michalewicz, Sridhar Isukapalli:
Pioneer: A New Tool for Coding of Multi-Level Finite State Machines Based on Evolution Programming. 105-116 - Youssef Saab, Cheng-Hua Chen:
An Effective Solution to the Linear Placement Problem. 117-129 - Wenjun Zhuang, Yong Ching Lim, Ganesh Samudra, Neng Yan:
A New Clustering Method Based on General Connectivity. 131-141 - Cheng-Hsi Chen, Ioannis G. Tollis:
Area Optimization of Slicing Floorplans in Parallel. 143-156 - Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh:
On the Minimum Density Interconnection Tree Problem. 157-169 - Yang Cai, D. F. Wong, Jason Cong:
Channel Density Minimization by Pin Permutation. 171-183
Volume 2, Number 3, 1994
- Chien-In Henry Chen:
Partitioning Techniques for Built-In Self-Test Design. 185-198 - Hyung Ki Lee, Dong S. Ha:
An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits. 199-207 - Fadi Busaba, Parag K. Lala:
Techniques for Self-Checking Combinational Logic Synthesis. 209-221 - Hassan Farhat, Steven G. From:
A Quadratic Programming Approach to Estimating the Testability and Random or Deterministic Coverage of a VLSl Circuit. 223-231 - C. P. Ravikumar, Haroon Rasheed:
TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing. 233-239 - Chi-Yu Mao, Yu Hen Hu:
SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm. 241-257 - Ausif Mahmood, Jayantha Herath, J. Jayasumana:
An Improved Data Flow Architecture for Logic Simulation Acceleration. 259-265 - Ali R. Hurson, Simin H. Pakzad:
Modular Scheme for Designing Special Purpose Associative Memories and Beyond. 267-286
Volume 2, Number 4, 1995
- Pradip K. Srimani:
Guest Editor's Introduction. i-ii - Susan R. Dickey, Richard Kenner:
Design of Components for a Low Cost Combining Switch. 287-303 - Peter W. Thompson, Julian D. Lewis:
The STC104 Packet Routing Chip. 305-314 - Kazuhiro Aoyama, Andrew A. Chien:
The Cost of Adaptivity and Virtual Lanes in a Wormhole Router. 315-333 - Sajal K. Das, Sabine R. Öhring, Amit K. Banerjee:
Embeddings into Hyper Petersen Networks: Yet Another Hypercube-Like Interconnection Topology. 335-351 - Isaac D. Scherson, Chi-Kai Chien:
Least Common Ancestor Networks. 353-364 - S. Q. Zheng, Bin Cong, Saïd Bettayeb:
Trade-Off Considerations in Designing Efficient VLSI Feasible Interconnection Networks. 365-374 - M. T. Raghunath, Abhiram Ranade:
Designing Interconnection Networks for Multi-level Packaging. 375-388 - Ke Qiu, Selim G. Akl:
On Some Properties of the Star Graph. 389-396
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-20 22:13 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
