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ORCIDMingyu Wang 0003
Person information
- affiliation: Sun Yat-sen University, School of Microelectronics Science and Technology, Guangzhou, China
Other persons with the same name
- Mingyu Wang (aka: MingYu Wang, Ming-Yu Wang, Ming-yu Wang) — disambiguation page
- Mingyu Wang 0001
![[0000-0001-5722-9752]](https://dblp.org/img/orcid-mark.12x12.png "0000-0001-5722-9752")
— Fudan University, School of Microelectronics, Shanghai, China - Mingyu Wang 0002 — Stanford University, Department of Mechanical Engineering, Stanford, CA, USA
- Mingyu Wang 0004 — Zhejiang University (ZJU), Hangzhou, China
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2020 – today
- 2025
[j5]Yao Qin, Mingyu Wang, Jiahua Yan, Tao Lu, Zhiyi Yu:
CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications. IEEE Trans. Circuits Syst. I Regul. Pap. 72(3): 1256-1268 (2025)- [j4]Haiqiu Huang, Mingyu Wang, Xiaojie Li, Baiqing Zhong, Zeqi Yang, Tao Lu, Yicong Zhang, Zhiyi Yu:
A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms. IEEE Trans. Circuits Syst. II Express Briefs 72(9): 1283-1287 (2025) - [c10]Renhao Fan, Yikai Cui, Weike Li, Mingyu Wang, Zhaolin Li:
MagiCache: A Virtual In-Cache Computing Engine. ISCA 2025: 1806-1818 - 2024
- [c9]Xiaojie Li, Mingyu Wang, Yangzhan Mai, Yicong Zhang, Baiqing Zhong, Zhiyi Yu:
BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM. ISVLSI 2024: 124-129 - [c8]Yukun Wei, Mingyu Wang, Haiqiu Huang, Wangguang Wang, Zhiyi Yu:
DAW-DMR: Divergence-Aware Warped DMR with Full Error Detection for GPGPU s. ISVLSI 2024: 161-166 - [c7]Yicong Zhang, Mingyu Wang, Wangguang Wang, Yangzhan Mai, Haiqiu Huang, Zhiyi Yu:
Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations. MICRO 2024: 671-685 - 2023
- [j3]Chuanghao Zhang, Mingyu Wang, Yangzhan Mai, Chengcheng Tang, Zhiyi Yu:
A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3589-3593 (2023) - [j2]Yicong Zhang, Mingyu Wang, Yangzhan Mai, Zhiyi Yu:
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2030-2043 (2023) - [c6]Wangguang Wang, Mingyu Wang, Yicong Zhang, Yukun Wei, Zhiyi Yu:
LWSDP: Locality-Aware Warp Scheduling and Dynamic Data Prefetching Co-design in the Per-SM Private Cache of GPGPUs. ICPADS 2023: 1230-1237 - [c5]Xiaoran Zhang, Mingyu Wang, Yicong Zhang, Tao Lu, Zhiyi Yu:
A Scalable Deadlock-Free Static Routing Algorithm for Chiplet-Based Systems. ICPADS 2023: 1350-1357 - [c4]Yangzhan Mai, Mingyu Wang, Chuanghao Zhang, Baiqing Zhong, Zhiyi Yu:
A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips. ISCAS 2023: 1-5 - [c3]Baiqing Zhong, Mingyu Wang, Chuanghao Zhang, Yangzhan Mai, Xiaojie Li, Zhiyi Yu:
A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference. ISVLSI 2023: 1-6 - [c2]Renhao Fan, Yikai Cui, Qilin Chen, Mingyu Wang, Youhui Zhang, Weimin Zheng, Zhaolin Li:
MAICC : A Lightweight Many-core Architecture with In-Cache Computing for Multi-DNN Parallel Inference. MICRO 2023: 411-423 - 2022
- [c1]Huafeng Ye, Huipeng Deng, Jian Wang, Mingyu Wang, Zhiyi Yu:
3D-NWA: A Nested-Winograd Accelerator for 3D CNNs. ICTA 2022: 143-144
2010 – 2019
- 2017
- [j1]Mingyu Wang, Zhaolin Li:
A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2419-2433 (2017)
Coauthor Index
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