"A Widely Linear, Power Efficient, Charge Controlled Delay Element for ..."

Raviteja Kammari, Vijaya Sankara Rao Pasupureddi (2019)

> Home

Details and statistics

DOI: 10.1007/978-981-32-9767-8_18

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vdat/KammariP19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vdat/KammariP19
Raviteja Kammari, Vijaya Sankara Rao Pasupureddi:
A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS. VDAT 2019: 202-214

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.