"An FPGA Accelerator With Efficient Weight Compression by Combining ..."

Yuanmiao Lin et al. (2025)

> Home

Details and statistics

DOI: 10.1109/TCSII.2025.3569589

access: closed

type: Journal Article

metadata version: 2025-11-18

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcasII/LinFLHZHCX25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcasII/LinFLHZHCX25
Yuanmiao Lin, Zhaozhang Feng, Xueming Li, Hongmin Huang, Ruidian Zhan, Xianghong Hu, Shuting Cai, Xiaoming Xiong:
An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization. IEEE Trans. Circuits Syst. II Express Briefs 72(11): 1595-1599 (2025)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.