"High-speed VLSI arithmetic processor architectures using hybrid number ..."

Hosahalli R. Srinivas, Keshab K. Parhi (1992)

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DOI: 10.1007/BF00925121

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type: Journal Article

metadata version: 2024-05-07

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Hosahalli R. Srinivas, Keshab K. Parhi:
High-speed VLSI arithmetic processor architectures using hybrid number representation. J. VLSI Signal Process. 4(2-3): 177-198 (1992)

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