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ORCIDASAP 1993: Venice, Italy
- International Conference on Application-Specific Array Processors, ASAP 1993, Proceedings, Venice, Italy, 25-27 October, 1993. IEEE 1993, ISBN 0-8186-3492-8
- Alain Darte, Yves Robert
:
Communication-minimal mapping of uniform loop nests onto distributed memory architectures. 1-14 - Antonio González, Miguel Valero-García:
The Xor embedding: An embedding of hypercubes onto rings and toruses. 15-28 - Lothar Thiele:
Resource constrained scheduling of uniform algorithm. 29-40 - Bilha Mendelson, Israel Koren:
Mapping algorithms onto a multiple-chip data-driven array. 41-52 - W. H. Chou, Sun-Yuan Kung:
Scheduling partitioned algorithms on processor arrays with limited communication supports. 53-64 - Lori E. Lucke, Keshab K. Parhi:
Parallel processing architectures for rank order and stack filters. 65-76 - R. Govindarajan, Guang R. Gao:
A novel framework for multi-rate scheduling in DSP applications. 77-88 - Stefan Bitterlich, Heinrich Meyr:
Efficient scalable architectures for Viterbi decoders. 89-100 - Georges Quénot, C. Coutelle, Jocelyn Sérot, Bertrand Y. Zavidovique:
A wavefront array processor for on the fly processing of digital video streams. 101-108 - Ed F. Deprettere, Richard Heusdens, Hendrik Theunis:
Subband filtering: Cordic modulation and systolic quadrature mirror filter tree. 109-123 - P. M. R. Jensen, K. Hermansen:
On synthesizing application-specific array architectures from behavioral specifications. 124-127 - Nam Ling:
A simple expert system for the reasoning of systolic designs. 128-131 - Frédéric Raimbault, Dominique Lavenier:
RELACS for systolic programming. 132-135 - Moreno Coli, Paolo Palazzari:
Data flow graphs granularity for overhead reduction within a PE in multiprocessor systems. 136-139 - Gerald G. Pechanek, José G. Delgado-Frias, Stamatis Vassiliadis:
A massively parallel diagonal-fold array processor. 140-143 - Kanad Ghose:
Response-pipelined CAM chips - Building blocks for large associated arrays. 144-147 - Antonella Bellettini, Alberto Ferrari, Roberto Guerrieri, Giorgio Baccarani:
An array-processor based architecture for classification problems. 148-151 - K. Müller, Frank Schirrmeister, Christian von Reventlow, Dirk Siebert, Jochen Reimers, C. Stoffers:
Realization of a real time phasecorrelation chipset used in a hierarchical two step HDTV motion vector estimator. 152-155 - Patricia Planet, Gilles Privat, Marc Renaudin:
Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms. 156-159 - C. H. John Ju, Herbert H. Taylor:
Mapping arbitrary projections for volume rendering onto an array processor. 160-163 - D. Camerani, M. Monacchi, R. Morbio:
M3: A high performance signal processor for RADAR applications. 164-167 - Martin Neschen:
COLUMNUS - An SIMD architecture for pattern recognition and simulations of statistical physics. 168-171 - Massimo Piccardi, Luigi Di Stefano, Rita Cucchiara, Tullio Salmon Cinotti:
Processing of variable size images on a cellular array: Performance analysis with the Abingdon Cross Benchmark. 172-175 - Yuh-Rong Leu, Ing-Yi Chen, Sy-Yen Kuo:
Matrix-matrix multiplications and fault tolerance on hypercube multiprocessors. 176-180 - Chie Dou:
A highly-parallel match architecture for AI production systems using application-specific associative matching processors. 180-183 - Eric Lemoine:
Reconfigurable hardware for molecular biology computing systems. 184-187 - Richard Conway, John Nelson:
Systolic design of a new finite field division/inverse algorithm. 188-191 - Giovanni Danese, Ivo De Lotto, D. Dotti, D. Lanterna, Francesco Leporati, Remo Lombardi, S. Romano:
Mapping Monte Carlo-Metropolis algorithm onto a double ring architecture. 192-195 - Barun K. Kar, R. C. K. Kumar, Dhiraj K. Pradhan:
An application specific processor for implementing stack filters. 196-199 - Wee-Chiew Tan, T.-Y. Meng:
Low-power polygon renderer for computer graphics. 200-213 - Shang-Hung Lin, Sun-Yuan Kung:
Volume rendering by wavefront architecture. 214-225 - Dharmavani Bhagavathi, Venkatavasu Bokka, Himabindu Gurla, Stephan Olariu, James L. Schwing, Ivan Stojmenovic, Jingyuan Zhang:
Time-optimal visibility-related algorithms on meshes with multiple broadcasting. 226-237 - Tanguy Risset, Siang Wun Song:
A real-time systolic algorithm for on-the-fly hidden surface removal. 238-249 - Hongchi Shi, Gerhard X. Ritter, Joseph N. Wilson:
An efficient algorithm for image-template product on SIMD mesh connected computers. 250-260 - Chris J. Scheiman, Peter R. Cappello:
A period-processor-time-minimal schedule for cubical mesh algorithms. 261-272 - Patrice Frison, Dominique Lavenier, Frédéric Raimbault:
I/O data management on SIMD systolic arrays. 273-284 - Sebastian Ritz, Matthias Pankert, V. Zivojinovic, Heinrich Meyr:
Optimum vectorization of scalable synchronous dataflow graphs. 285-296 - Jingling Xue:
A new formulation of the mapping conditions for the synthesis of linear systolic arrays. 297-308 - Francesco Gregoretti, Claudio Sansoè, Leonardo M. Reyneri, Alberto Broggi, Gianni Conte:
The PAPRICA SIMD array: Critical reviews and perspectives. 309-320 - Zheng Zhou, Wayne P. Burleson:
Formal descriptions, semantics and verification of VLSI array processors. 321-332 - Qutaibah M. Malluhi, Magdy A. Bayoumi, T. R. N. Rao:
An application-specific array architecture for feedforward with backpropagation ANNs. 333-344 - Paolo Ienne, Marc A. Viredaz:
GENES IV: A bit-serial processing element for a built-model neural-network accelerator. 345-356 - Alfred Strey:
Implementation of large neural associative memories by massively parallel array processors. 357-368 - Richard P. Brent, Andrew Tridgell:
A fast, storage-efficient parallel sorting algorithm. 369-379 - Rong Lin, Stephan Olariu:
A practical constant time sorting network. 380-391 - Yuepeng Zheng, Sayfe Kiaei:
Multi-rate transformation of directional affine recurrence equations. 392-403 - Zhaoyun Xing, Weijia Shang:
An algorithm for accurate data dependence test. 404-415 - Michel Auguin, Fernand Boéri, C. Carrière, G. Menez:
Synthesis of dedicated SIMD processors. 416-427 - Donald G. Baltus, Jonathan Allen:
Efficient exploration of nonuniform space-time transformations for optimal systolic array synthesis. 428-441 - Bongjin Jung, Wayne P. Burleson:
Node merging: A transformation on bit-level dependence graphs for efficient VLSI array design. 442-453 - Miodrag Potkonjak, Lisa M. Guerra, Jan M. Rabaey:
Heterogeneous BISR techniques for yield and reliability enhancement using high level synthesis transformations. 454-465 - Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Digit systolic algorithms for fine-grain architectures. 466-477 - K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.:
Reduced area multipliers. 478-489 - B. Koppenhofer:
A novel architecture for a decision-feedback equalizer using extended signal-digit feedback. 490-501 - Tudor Jebelean:
Systolic normalization of rational numbers. 502-513 - S. P. Johansen:
Systolic evaluation of functions: Digit-level algorithm and realization. 514-525 - Jean-Claude Bajard, Alain Guyot, Jean-Michel Muller, Ali Skaf:
Design of a VLSI circuit for on-line evaluation of several elementary functions using their Taylor expansions. 526-535 - Yongjin Jeong, Wayne P. Burleson:
VLSI array synthesis for polynomial GCD computation. 536-547 - Rumen Andonov, Sanjay V. Rajopadhye:
An optimal algo-tech-cuit for the knapsack problem. 548-559 - Luc de Vos, Matthias Schöbinger:
Efficient architecture of a programmable block matching processor. 560-571 - Dominique Houzet, K. Fatni:
A 1D linearly expandable interconnection network performance analysis. 572-582 - Darren Patrick Rodohan, S. R. Saunders:
A CAD tool for electromagnetic simulation on the associative string processor. 583-592
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