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ORCID11. ACM Great Lakes Symposium on VLSI 2001: West Lafayette, Indiana, USA
- Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh:
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001. ACM 2001, ISBN 1-58113-351-0 - Leila Barakatain, Sofiène Tahar, Jean Lamarche, Jean-Marc Gendreau:
Practical approaches to the verification of a telecom megacell using FormalCheck. 1-6 - Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
A novel reseeding technique for accumulator-based test pattern generation. 7-12 - Irith Pomeranz, Sudhakar M. Reddy:
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. 13-18 - Florin Balasa, Werner Geurts, Francky Catthoor, Hugo De Man:
Solving large scale assignment problems in high-level synthesis by approximative quadratic programming. 19-24 - Abhishek Ranjan, Ankur Srivastava, V. Karnam, Majid Sarrafzadeh:
Layout aware retiming. 25-30 - Zhong Wang, Edwin Hsing-Mean Sha, Yuke Wang:
Optimal partitioning and balanced scheduling with the maximal overlap of data footprints. 31-36 - Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang:
SOI for asynchronous dynamic circuits. 37-42 - Ram Krishnamurthy, Mark A. Anders, Krishnamurthy Soumyanath, Shekhar Borkar:
Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. 43-44 - Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara:
Challenges in integrated CMOS transceivers for short distance wireless. 45-50 - Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung:
An accurate evaluation of routing density for symmetrical FPGAs. 51-55 - Mehmet Can Yildiz, Patrick H. Madden:
Preferred direction Steiner trees. 56-61 - Hung-Ming Chen, D. F. Wong
, Wai-Kei Mak, Hannah Honghua Yang:
Faster and more accurate wiring evaluation in interconnect-centric floorplanning. 62-67 - Mehmet Can Yildiz, Patrick H. Madden:
Global objectives for standard cell placement. 68-72 - Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook:
A circuit level implementation of an adaptive issue queue for power-aware microprocessors. 73-78 - Bipul Das, Swapna Banerjee:
A CORDIC based array architecture for complex discrete wavelet transform. 79-84 - José G. Delgado-Frias, Girish B. Ratanpal:
A VLSI wrapped wave front arbiter for crossbar switches. 85-88 - Edward Ahn, Seung-Moon Yoo, Sung-Mo Kang:
Effective algorithms for cache-level compression. 89-92 - Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang:
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. 93-96 - Malay K. Ganai, Adnan Aziz:
Rarity based guided state space search. 97-102 - Chih-Wei Jim Chang, Malgorzata Marek-Sadowska:
Who are the alternative wires in your neighborhood? (alternative wires identification without search). 103-108 - Yu-Min Lee, Charlie Chung-Ping Chen:
Hierarchical model order reduction for signal-integrity interconnect synthesis. 109-114 - Min Xu, Lei He:
An efficient model for frequency-dependent on-chip inductance. 115-120 - Lijun Gao, Keshab K. Parhi:
Models for power consumption and power grid noise due to datapath transition activity. 121-126 - Deepak Srivastava:
Electronic devices, structures and transport in carbon based materials: molecular electronics and quantum computing. 127 - Mark C. Hersam:
Single molecule electronics. 128 - John P. Denton, Sang Woo Pae, Gerold W. Neudeck:
Vertical integration of submicron MOSFETs in two separate layers of SOI islands formed by silicon epitaxial lateral overgrowth. 129-132 - Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Transistor sizing for reliable domino logic design in dual threshold voltage technologies. 133-138 - José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas:
Practical low-cost CPL implementations threshold logic functions. 139-144 - Adimathara P. Preethy, Damu Radhakrishnan, Amos Omondi:
A high performance RNS multiply-accumulate unit. 145-148 - Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka:
A fast hybrid carry-lookahead/carry-select adder design. 149-152
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