This letter presents a 5.2-6.4 GHz fractional-N phase-locked loop (PLL) with low in-band fractional spurs. The proposed probability-distribution-shaping delta-sigma modulator (PDS-DSM) reduces the in-band fractional spurs arising from loop nonlinearity by changing the probability distribution of the DSM. The enhanced PDS-DSM is realized by integrating the PDS dither with a multi-mode filter at the output stage of a conventional MASH 1-1-1 architecture. The proposed PLL was fabricated in a 65 nm CMOS process. Notably, with the incorporation of second-order and third-order filtered PDS dithers in the PDS-DSM, in-band fractional spurs at 10 kHz offset from 5.825 GHz were reduced from -49.5 dBc to -58.2 dBc and -62.8 dBc respectively.