xapp1222-idf-for-7s-or-zynq-vivado_中英文对照版_2025年.pdf

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Summary

This application note describes how to implement security- or safety-critical designs using the

Xilinx® Isolation Design Flow (IDF) with the Xilinx Vivado® Design Suite. Design applications

include information assurance (single chip cryptography), avionics, automotive, and industrial.

This document explains how to:

• Implement isolated functions in a single Xilinx 7 series FPGA or Zynq®-7000 SoCs

IDF that meets fail-safe and physical security requirements for high-assurance applications. If

you wish to add additional security to your design, the Security Monitor IP, developed by Xilinx,

can be purchased. If you embed this IP, modifications to the steps in this document must be

made as described in Integration and Verification of Security Monitor 3.0 for 7 Series FPGAs and

Zynq-7000 All Programmable SoC (XAPP796). Refer to the Aerospace and Defense Security

Monitor IP Core Product Marketing Brief

[Ref 1] or contact your local Xilinx representative for

to using the Xilinx ISE® Design Suite for developing IDF designs for the 7 series FPGA devices

and Zynq-7000 SoC devices. The rules for IDF defined in this application note do not differ from

those defined in XAPP1086, but the methodology for implementation using Vivado tools does.

Application Note: 7 Series and Zynq-7000 SoC Devices

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detailed information about the design files, see

Introduction

safety-critical functions. The successful completion of the Xilinx Isolation Design Flow has

single FPGA is made possible through Xilinx isolation technology. Special attributes such as

HD.ISOLATED and the features it enables are necessary to provide controls to achieve the

Zynq®-7000 SoC family Supported

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Ownership (physical/logical)—The concept of physical versus logical ownership is an

section

Trusted Routing Design Guidelines.

Function—A collection of logic that performs a specific operation (example: an AES

encryptor).

Logic—Circuits used to implement a specific function (examples are: flip-flop, look up table,

RAM, to name a few).

Isolated Region/Pblock—A physical area to implement logic.

tion regions

- It does not come within one fence tile from another unintended isolation region

Figure 1. Example routes excluded for programmable

isolation regions are shown.

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