Intel8086手册_intel手册,intel手册中文版pdf资源-CSDN下载

需积分: 21 17 浏览量 2023-12-12 09:47:12 上传评论收藏 629KB PDF 举报

Intel 8086 手册，PDF版。 16-BIT HMOS MICROPROCESSOR 8086/8086-2/8086-1 其他下载链接 https://pdf1.alldatasheetcn.com/datasheet-pdf/download/1154707/INTEL/8086.html The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations ... 所有权利归Intel所有，仅供学习交流之用。《Intel 8086手册》是一份详细的技术文档，主要介绍了Intel 8086处理器的特性、架构以及操作模式。8086是一款16位高性能的微处理器，适用于1990年9月的技术环境。它采用N沟道耗尽型负载硅门技术（HMOS-III），并封装在40引脚的CERDIP或塑料封装中，以适应不同速度需求，提供5、8和10MHz三种时钟频率的版本。 8086处理器的核心特性包括其直接寻址能力，能够处理1MB的内存。它的设计旨在支持强大的汇编语言和高效的高级语言，拥有14个16位寄存器，并且支持对称操作。此外，它还提供了24种操作数寻址模式，支持位、字节、字和块操作，无论是8位还是16位，无论是有符号还是无符号的二进制或十进制运算，包括乘法和除法功能。处理器的引脚配置对于理解其工作原理至关重要。如图2所示，8086有40个引脚，每个引脚都有特定的功能描述，例如AD15-AD0是数据/地址总线，它们在不同的时钟周期内作为地址或数据传输线。A0引脚用于区分数据总线的低八位，当进行低字节传输时，A0为低电平。 8086处理器可以工作在单处理器和多处理器配置下，以实现高水平的性能。在最小模式和最大模式下，8086系统都能通过“局部总线”与处理器直接连接，这个局部总线不考虑额外的总线缓冲器。在中断应答和局部总线“保持应答”期间，数据/地址总线会变为三态关闭，即线路不驱动任何信号。此外，8086还兼容MULTIBUS系统接口，这意味着它可以与其他符合MULTIBUS标准的设备无缝集成。根据温度范围的不同，8086有标准温度范围（EXPRESS）和扩展温度范围两种版本，分别适用于不同的应用环境。总结起来，Intel 8086是一款灵活、功能强大的16位处理器，具有丰富的寻址模式、操作类型和兼容性，适合于构建复杂系统和进行高效计算。这份手册对于深入理解8086的硬件特性和软件开发至关重要，是学习和研究8086微处理器的宝贵资源。

资源推荐

资源详情

资源评论

September 1990 Order Number: 231455-005

8086

16-BIT HMOS MICROPROCESSOR

8086/8086-2/8086-1

Direct Addressing Capability 1 MByte

of Memory

Architecture Designed for Powerful

Assembly Language and Efficient High

Level Languages

14 Word, by 16-Bit Register Set with

Symmetrical Operations

24 Operand Addressing Modes

Bit, Byte, Word, and Block Operations

8 and 16-Bit Signed and Unsigned

Arithmetic in Binary or Decimal

Including Multiply and Divide

Range of Clock Rates:

5 MHz for 8086,

8 MHz for 8086-2,

10 MHz for 8086-1

MULTIBUS System Compatible

Interface

Available in EXPRESS

– Standard Temperature Range

– Extended Temperature Range

Available in 40-Lead Cerdip and Plastic

Package

(See Packaging Spec. Order

›

231369)

The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is

implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin

CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations

to achieve high performance levels.

231455–1

Figure 1. 8086 CPU Block Diagram

231455–2

40 Lead

Figure 2. 8086 Pin

Configuration

8086

Table 1. Pin Description

The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ‘‘Local

Bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to

additional bus buffers).

Symbol Pin No. Type Name and Function

–AD

2– 16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed

memory/IO address (T

), and data (T

) bus. A

analogous to BHE

for the lower byte of the data bus, pins D

–D

. It is

LOW during T

when a byte is to be transferred on the lower portion

of the bus in memory or I/O operations. Eight-bit oriented devices tied

to the lower half would normally use A

to condition chip select

functions. (See BHE.) These lines are active HIGH and float to 3-state

OFF during interrupt acknowledge and local bus ‘‘hold acknowledge’’.

, 35– 38 O ADDRESS/STATUS: During T

these are the four most significant

address lines for memory operations. During I/O operations these

lines are LOW. During memory and I/O operations, status information

is available on these lines during T

. The status of the

interrupt enable FLAG bit (S

) is updated at the beginning of each

CLK cycle. A

and A

are encoded as shown.

This information indicates which relocation register is presently being

used for data accessing.

These lines float to 3-state OFF during local bus ‘‘hold acknowledge.’’

Characteristics

0 (LOW) 0 Alternate Data

0 1 Stack

1 (HIGH) 0 Code or None

1 1 Data

is 0

(LOW)

BHE/S

34 O BUS HIGH ENABLE/STATUS: During T

the bus high enable signal

(BHE

) should be used to enable data onto the most significant half of

the data bus, pins D

–D

. Eight-bit oriented devices tied to the upper

half of the bus would normally use BHE to condition chip select

functions. BHE

is LOW during T

for read, write, and interrupt

acknowledge cycles when a byte is to be transferred on the high

portion of the bus. The S

status information is available during T

, and T

. The signal is active LOW, and floats to 3-state OFF in

‘‘hold’’. It is LOW during T

for the first interrupt acknowledge cycle.

BHE A

Characteristics

0 0 Whole word

0 1 Upper byte from/to odd address

1 0 Lower byte from/to even address

1 1 None

RD 32 O READ: Read strobe indicates that the processor is performing a

memory or I/O read cycle, depending on the state of the S

pin. This

signal is used to read devices which reside on the 8086 local bus. RD

is active LOW during T

and T

of any read cycle, and is

guaranteed to remain HIGH in T

until the 8086 local bus has floated.

This signal floats to 3-state OFF in ‘‘hold acknowledge’’.

8086

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

READY 22 I READY: is the acknowledgement from the addressed memory or I/O

device that it will complete the data transfer. The READY signal from

memory/IO is synchronized by the 8284A Clock Generator to form

READY. This signal is active HIGH. The 8086 READY input is not

synchronized. Correct operation is not guaranteed if the setup and hold

times are not met.

INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled

during the last clock cycle of each instruction to determine if the

processor should enter into an interrupt acknowledge operation. A

subroutine is vectored to via an interrupt vector lookup table located in

system memory. It can be internally masked by software resetting the

interrupt enable bit. INTR is internally synchronized. This signal is

active HIGH.

TEST 23 I TEST: input is examined by the ‘‘Wait’’ instruction. If the TEST input is

LOW execution continues, otherwise the processor waits in an ‘‘Idle’’

state. This input is synchronized internally during each clock cycle on

the leading edge of CLK.

NMI 17 I NON-MASKABLE INTERRUPT: an edge triggered input which causes

a type 2 interrupt. A subroutine is vectored to via an interrupt vector

lookup table located in system memory. NMI is not maskable internally

by software. A transition from LOW to HIGH initiates the interrupt at the

end of the current instruction. This input is internally synchronized.

RESET 21 I RESET: causes the processor to immediately terminate its present

activity. The signal must be active HIGH for at least four clock cycles. It

restarts execution, as described in the Instruction Set description, when

RESET returns LOW. RESET is internally synchronized.

CLK 19 I CLOCK: provides the basic timing for the processor and bus controller.

It is asymmetric with a 33% duty cycle to provide optimized internal

timing.

40 V

5V power supply pin.

GND 1, 20 GROUND

MN/MX 33 I MINIMUM/MAXIMUM: indicates what mode the processor is to

operate in. The two modes are discussed in the following sections.

The following pin function descriptions are for the 8086/8288 system in maximum mode (i.e., MN/MX

Only the pin functions which are unique to maximum mode are described; all other pin functions are as

described above.

26– 28 O STATUS: active during T

, and T

and is returned to the passive state

(1, 1, 1) during T

or during T

when READY is HIGH. This status is used

by the 8288 Bus Controller to generate all memory and I/O access control

signals. Any change by S

, or S

during T

is used to indicate the

beginning of a bus cycle, and the return to the passive state in T

or T

used to indicate the end of a bus cycle.

8086

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

26– 28 O These signals float to 3-state OFF in ‘‘hold acknowledge’’. These status

lines are encoded as shown.

(Continued)

Characteristics

0 (LOW) 0 0 Interrupt Acknowledge

0 0 1 Read I/O Port

0 1 0 Write I/O Port

0 1 1 Halt

1 (HIGH) 0 0 Code Access

1 0 1 Read Memory

1 1 0 Write Memory

1 1 1 Passive

RQ/GT

, 30, 31 I/O REQUEST/GRANT: pins are used by other local bus masters to force

the processor to release the local bus at the end of the processor’s

/GT

current bus cycle. Each pin is bidirectional with RQ/GT

having higher

priority than RQ

/GT

. RQ/GT pins have internal pull-up resistors and

may be left unconnected. The request/grant sequence is as follows

(see Page 2-24):

1. A pulse of 1 CLK wide from another local bus master indicates a local

bus request (‘‘hold’’) to the 8086 (pulse 1).

2. During a T

or T

clock cycle, a pulse 1 CLK wide from the 8086 to

the requesting master (pulse 2), indicates that the 8086 has allowed the

local bus to float and that it will enter the ‘‘hold acknowledge’’ state at

the next CLK. The CPU’s bus interface unit is disconnected logically

from the local bus during ‘‘hold acknowledge’’.

3. A pulse 1 CLK wide from the requesting master indicates to the 8086

(pulse 3) that the ‘‘hold’’ request is about to end and that the 8086 can

reclaim the local bus at the next CLK.

Each master-master exchange of the local bus is a sequence of 3

pulses. There must be one dead CLK cycle after each bus exchange.

Pulses are active LOW.

If the request is made while the CPU is performing a memory cycle, it

will release the local bus during T

of the cycle when all the following

conditions are met:

1. Request occurs on or before T

2. Current cycle is not the low byte of a word (on an odd address).

3. Current cycle is not the first acknowledge of an interrupt acknowledge

sequence.

4. A locked instruction is not currently executing.

If the local bus is idle when the request is made the two possible events

will follow:

1. Local bus will be released during the next clock.

2. A memory cycle will start within 3 clocks. Now the four rules for a

currently active memory cycle apply with condition number 1 already

satisfied.

LOCK 29 O LOCK: output indicates that other system bus masters are not to gain

control of the system bus while LOCK

is active LOW. The LOCK signal

is activated by the ‘‘LOCK’’ prefix instruction and remains active until the

completion of the next instruction. This signal is active LOW, and floats

to 3-state OFF in ‘‘hold acknowledge’’.

8086

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

, QS

24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after

which the queue operation is performed.

and QS

provide status to allow external tracking of the internal

8086 instruction queue.

Characteristics

0 (LOW) 0 No Operation

0 1 First Byte of Op Code from Queue

1 (HIGH) 0 Empty the Queue

1 1 Subsequent Byte from Queue

The following pin function descriptions are for the 8086 in minimum mode (i.e., MN/MX

). Only the pin

functions which are unique to minimum mode are described; all other pin functions are as described above.

M/IO 28 O STATUS LINE: logically equivalent to S

in the maximum mode. It is used to

distinguish a memory access from an I/O access. M/IO

becomes valid in

the T

preceding a bus cycle and remains valid until the final T

of the cycle

HIGH, IO

LOW). M/IO floats to 3-state OFF in local bus ‘‘hold

acknowledge’’.

WR 29 O WRITE: indicates that the processor is performing a write memory or write

I/O cycle, depending on the state of the M/IO

signal. WR is active for T

and T

of any write cycle. It is active LOW, and floats to 3-state OFF in

local bus ‘‘hold acknowledge’’.

INTA 24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active

LOW during T

and T

of each interrupt acknowledge cycle.

ALE 25 O ADDRESS LATCH ENABLE: provided by the processor to latch the

address into the 8282/8283 address latch. It is a HIGH pulse active during

of any bus cycle. Note that ALE is never floated.

DT/R 27 O DATA TRANSMIT/RECEIVE: needed in minimum system that desires to

use an 8286/8287 data bus transceiver. It is used to control the direction of

data flow through the transceiver. Logically DT/R

is equivalent to S

in the

maximum mode, and its timing is the same as for M/IO

. (T

HIGH, R

LOW.) This signal floats to 3-state OFF in local bus ‘‘hold acknowledge’’.

DEN 26 O DATA ENABLE: provided as an output enable for the 8286/8287 in a

minimum system which uses the transceiver. DEN is active LOW during

each memory and I/O access and for INTA cycles. For a read or INTA

cycle

it is active from the middle of T

until the middle of T

, while for a write cycle

it is active from the beginning of T

until the middle of T

. DEN floats to 3-

state OFF in local bus ‘‘hold acknowledge’’.

HOLD, 31, 30 I/O HOLD: indicates that another master is requesting a local bus ‘‘hold.’’ To be

acknowledged, HOLD must be active HIGH. The processor receiving the

HLDA

‘‘hold’’ request will issue HLDA (HIGH) as an acknowledgement in the

middle of a T

or T

clock cycle. Simultaneous with the issuance of HLDA

the processor will float the local bus and control lines. After HOLD is

detected as being LOW, the processor will LOWer the HLDA, and when the

processor needs to run another cycle, it will again drive the local bus and

control lines. Hold acknowledge (HLDA) and HOLD have internal pull-up

resistors.

The same rules as for RQ

/GT apply regarding when the local bus will be

released.

HOLD is not an asynchronous input. External synchronization should be

provided if the system cannot otherwise guarantee the setup time.

剩余29页未读，继续阅读

评论收藏

内容反馈

a654651231

粉丝: 0

Intel 8086 手册

IntelCPU机器指令中文版手册汇编.pdf

intel8088datasheet

8086汇编手册

Intel8086用户手册

Intel 参考手册 三卷全

INTEL 架构 8086指令详解 指令集

8086汇编指令集[借鉴].pdf

Intel手册（8086、8237A、8251、8254、8255、8259)

2025最新英特尔手册完整中文版

Intel 8086 手册1

8086intel指令集手册第一卷

8086 CPU手册

完整版_8086汇编手册查询

INTEL-8086-datasheet.pdf

intel开发手册 全5册

intel100系列芯片组数据手册1

intel的主板芯片8系列手册

intel8086.pdf

Intel 64及IA-32 架构软件开发者手册(1~3卷).zip

Intel手册完整版三册全

intel开发手册.zip

intel 软件开发人员手册

INTEL开发手册卷3(中文版)

英特尔FPGA手册目录

Intel CPU 手册

INTEL指令参考手册-manual(高清文字版)

Intel官方手册

英特尔_64和IA-32体系结构软件开发者的手册[PDF]

8086汇编帮助手册(chm)

Intel开发者手册_第二卷_指令集手册

MySQL, Zookeeper, Redis 分布式锁

java sql语句类命名规范

最新资源

Intel 参考手册三卷全

INTEL 架构 8086指令详解指令集

intel开发手册全5册