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KCU116原理图 PDF版本

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该文档是xilinx官网提供的KCU116 DXDesigner原理图的PDF版本。该文档是xcku5p参考开发板,其中包括系统启动、时钟、电源、PCIE、GPIO、DDR4、以太网、IIC等设计,为硬件设计者提供参考。
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XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC,
AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE IN
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YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST,
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DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR
ASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE
THE DOCUMENTATION.
THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")
ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH
CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY
DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT
IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET.
ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY
APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY
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THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
DISCLAIMER:
HW-U1-KCU116 Evaluation Board
(XCKU5P-FFVB676)
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TITLE:
DATE: 1.0
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04/04/2017:05:22
PCB P/N: 1280924
TEST P/N: TSSXXXX
SCH P/N: 0381757
ASSY P/N: 0432019
601
Title Page
SCHEM, ROHS COMPLIANT
HW-U1-KCU116_REV1_0
Title Page

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PCB P/N: 1280924
TEST P/N: TSSXXXX
SCH P/N: 0381757
ASSY P/N: 0432019
602
Block Diagram
SCHEM, ROHS COMPLIANT
HW-U1-KCU116_REV1_0
12VDC
Clock devices
Pages 36-37
System
0
HP
BANK# PAGE#
BANK 0
BANK#
PROG. PB
Page 17
PAGE#
INIT,DONE LEDs
67
HP
66
65
BANK 87
BANK 84
U1
BANK 86
5
3
BANK 64
PWR BANKS
7
6
7
XCKU5P-FFVB676
Page 60
12-14
DDR4 Comp. Memory
Pages 18-19
MECHANICALSJTAG CONN.
HP
GTY227
32-bit: 2 x 16-bit
MT40A256M16GE-075E
BANK 65
8
VCCINT @ 40A
UTIL_3V3 @ 20A
DDR4 VTT @ 3A
Pages 45-54
Page 57
UTIL_2V5 @ 2A
Page 58
VTT Source/sink LDO:
Page 57
SYS_1V8 @ 1A
Page 57
SYS_1V0 @ 2A
Page 55
PMBUS UTIL RAIL
FMC HPC0 Connector
Page 21-24
8-LANE PCIE
Page 20
HDMI Page 29-30
Page 40
Ethernet PHY
Page 39
86
HD
87
HD
64
HP
84
HD
0
FMC0 DP[0:3]
Page 21
Page 41
Page 38
ZSFP 1x4 Cage
Pages 26-27
GTY224
Page 28
GTY226
GTY225
GTY224
Ironwood Socket P/N: C11090-D5616
ZSFP x4 CONNECTORS
BANK 66
BANK 67
9
9
GTY225
10
10
GTY226
GTY227
11
11
PWR DECOUPLING 15-16
EDGE CONNECTOR
QSPI0
SYSMON HDR.
Page 4
Page 3
Page 31-35 Page 42
Page 43
PB, DIP SWITCHES
LEDS PMOD
LEDS (Page 40)
zSFP CTRL
QSPI1
USB UART
IIC MAIN
Page 6
Page 26-27
Page 39
Page 42
Block Diagram
zSFP Clock
Fixed and
System Controller
and SD Card Socket
IIC EEPROM
2 x IIC MUX
I/O EXPANDER
(IIC MAIN)
PMBUS Hdr.
Level-Shifters
Page 44
Page 25
Blank Page
Programmable
Recovery
VCC3V3 @ 5A
VCC1V8 @ 3A
VCC1V2 @ 2A
VCCAUX @ 3A
VCCBRAM @ 6A
MGTVCCAUX @ 1A
MGTAVTT @ 6A
MGTAVCC @ 6A
VADJ_FMC @ 10A
SYS_5V0 @ 1A
Page 56

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TITLE:
DATE: 1.0
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04/04/2017:05:22
PCB P/N: 1280924
TEST P/N: TSSXXXX
SCH P/N: 0381757
ASSY P/N: 0432019
603
FPGA Bank 0
SCHEM, ROHS COMPLIANT
HW-U1-KCU116_REV1_0
POR_OVERRIDE select
Default: 2-3 GND
FPGA Bank 0
SYSMON_DXN
SYSMON_DXP
SYSMON_VP_R
SYSMON_VN_R
GND
1%
4.70K
R94
1
2
GND
1
2
3
HDR_1X3
J85
VCCINT
GND
R397
1.00K
1%
1
2
2
1
DNP
DNP
R291
L16
2
1
FERRITE-600
C902
2
1
0.47UF
10V
SYSMON_AGND
1
2
C1
0.1UF
25V
FPGA_SYSMON_AVCC
FERRITE-600
1
2
L17
GND
VCCAUX
SYSMON_AGND
GND
IN OUT
GND
REF3012
SYSMON_AGND
1
2
FERRITE-600
L55
SYSMON_AGND
1
2
3
HDR_1X3
J90
1 2
3
SOT23_3
IC VOLT REF, 1.25V
U64
1
2
C384
10UF
10V
1
2
0.47UF
C492
10V
SYSMON_VREFP
FPGA_SYSMON_AVCC
1/16W
C25
0.1UF
25V2
1
GND
2
1
3
D40
BAS40-04
40V
200MW
NC
SYS_1V8
VCC_VBATT
2
1
BAT_TS518_TS621_DUAL
B1
TS518FE_FL35E
2
1
1%
4.70K
R22
1/16W
VCC_VBATT
SYSMON_VREFP
SYSMON_AGND
JTAG_TCK
JTAG_TMS
JTAG_TDI
FPGA_TDO_FMC_TDI
FPGA_DONE
FPGA_INIT_B
FPGA_PROG_B
FPGA_M2
GND
VCC1V8
VCC1V8_BUS
QSPI_CLK
QSPI0_DQ2
QSPI0_DQ0
QSPI0_DQ3
QSPI0_DQ1
QSPI0_CS_B
GND
POR_OVERRIDE
PUDC_B
R1172
20
1/16W
1%
1
2
C1264
33PF
50V
C0G, NP0
2
1
R1179
1
2
1.00K
1/16W
1%
GND
1%
1/16W
1.00K
2
1
R1180
VCC1V8
GND
P3
P1
P4
P2
Pushbutton
VCC1V8_BUS
2
1
1/16W
R14
4.70K
1%
3
1
4
2
TL3301EF100QG
SW5
1.8V
FPGA_PROG_B
SYSMON_VREF
VCCO_0_AA11
VCCO_0_AD12
M0_0_AA10
M1_0_AA9
M2_0_AF12
D00_MOSI_0_AD11
D01_DIN_0_AC12
D02_0_AC11
D03_0_AE11
DONE_0_AB11
RSVDGND_W11
PROGRAM_B_0_AB9
INIT_B_0_W10
TDI_0_AB12
TDO_0_Y10
TMS_0_AB10
TCK_0_AE12
CCLK_0_Y11
VBATT_Y9
VN_R13
VP_P14
VREFP_R14
VREFN_P13
GNDADC_N13
VCCADC_N14
DXN_T13
DXP_T14
RDWR_FCS_B_0_AA12
POR_OVERRIDE_Y12
PUDC_B_0_W9
XCKU5PFFVB676
BANK 0
U1
W9
Y12
AA12
T14
T13
N14
N13
P13
R14
P14
R13
Y9
Y11
AE12
AB10
Y10
AB12
W10
AB9
W11
AB11
AE11
AC11
AC12
AD11
AF12
AA9
AA10
AD12
AA11
SOC_676_1MM_IRON
SOC_DK5_FFVB676_IRONWOOD

A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE: 1.0
01
DN
04/04/2017:05:22
PCB P/N: 1280924
TEST P/N: TSSXXXX
SCH P/N: 0381757
ASSY P/N: 0432019
604
SYSMON Hdr INIT DONE LED QSPI0
SCHEM, ROHS COMPLIANT
HW-U1-KCU116_REV1_0
SYSMON Hdr INIT DONE LED QSPI0
GNDGND
GND
GND
GND
GND
GRN
RED
DIR
VCCB
B
VCCA
GND
A
DIR
VCCB
B
VCCA
GND
A
VCC1V8_BUS
VCC1V8_BUS UTIL_3V3
UTIL_3V3 UTIL_3V3
1
2
C86
0.1UF
25V
1
2
C87
0.1UF
25V
1
2
C181
0.1UF
25V
34
1 2
LED-GRN-RED
DS1
2 1
LED-GRN-SMT
DS32
2
1
1%
4.70K
R13
1/16W
2
1
1%
4.70K
R15
1/16W
2
1
1%
261
R323
1/10W
2
1
R326
261
1%
1/10W
2
1
1/10W
1%
261
R328
5
6
4
1
2
3
U43
SC70_6
SN74AVC1T45
5
6
4
1
2
3
U44
SC70_6
SN74AVC1T45
1
2
C183
0.1UF
25V
INIT_B = 0, RED LED ON
INIT_B = 1, GRN LED ON
DONE_0 = 0, DONE LED OFF
DONE_0 = 1, DONE LED ON
FPGA_DONE
FPGA_INIT_B
2
1
1%
100
R432
2
1
R433
100
1%
1
2
C408
2700PF
50V
SYSMON_VN
SYSMON_VPSYSMON_VP_R
SYSMON_VN_R
1 2
3
5 6
7 8
9 10
4
1211
J93
70246-1201
SYSMON_AGND
SYSMON_DXN
SYSMON_DXPNC
NC
VCCINT_VIN_R_N VCCINT_VIN_R_P
SYSMON_VREF FPGA_SYSMON_AVCC
SYSMON_VN SYSMON_VP
SYSMON HEADER
GND
GND
2
1
DNP
R290
SYSMON_VP_R_I2C
SYSMON I2C Address jumpers
SYSMON_VN_R_I2C
1
2
J12
HDR_1X2
SYSMON_VP_R
SYSMON_VN_R1
2
HDR_1X2
J13
2
1
1%
20.5K
R132
1%
20.5K
R133
2
1
VCCAUX
GND
GND
GND
VCC
VSS
C
DQ0
S_B
DQ2_VPP_WP_B
DQ3_HOLD_B
DQ1
RESET_B
NC1
NC2
NC3
NC7
NC6
NC4
NC5
VCC1V8
1
2
C23
0.1UF
25V
VCC1V8
2
1
DNP
R97
1
2
0.1UF
C24
25V
VCC1V8
2
1
1/10W
5%
0
R107
2
1
R98
DNP
UTIL_3V3
2
1
1%
1/10W
2.40K
R5
QSPI_CLK
QSPI0_DQ1
NC
NC
NCNC
NC
NC
QSPI0_CS_B
QSPI0_VIO
QSPI0_DQ0
QSPI0_DQ3
QSPI0_DQ2
QSPI0_VCC
2
10
16
15
7
9
1
8
3
4
5
6
14
13
11
12
MT25QU01GBBB8ESF-0SIT
SO16_50P300X413
U2
2
1
1/16W
R10
4.70K
1%
2
1
1/16W
R11
4.70K
1%
QSPI_RESET_B
DNP
R115
1
2

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C
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1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE: 1.0
01
DN
04/04/2017:05:22
PCB P/N: 1280924
TEST P/N: TSSXXXX
SCH P/N: 0381757
ASSY P/N: 0432019
605
FPGA Banks 64 FMC
SCHEM, ROHS COMPLIANT
HW-U1-KCU116_REV1_0
FPGA Banks 64 FMC
Underneath the FPGA via array
right next to the via
Layout: Place resistor and capacitor for VREF
VADJ_FMC
GND
R984
DNP
2
1
C1211
DNP
2
1
FMC_HPC0_VREF_A_M2C
FMC_HPC0_LA05_N
FMC_HPC0_LA05_P
FMC_HPC0_LA06_N
FMC_HPC0_LA06_P
FMC_HPC0_LA02_P
FMC_HPC0_LA02_N
FMC_HPC0_LA04_P
FMC_HPC0_LA04_N
FMC_HPC0_LA03_N
FMC_HPC0_LA03_P
FMC_HPC0_LA07_P
FMC_HPC0_LA07_N
FMC_HPC0_LA09_N
FMC_HPC0_LA09_P
FMC_HPC0_LA10_N
FMC_HPC0_LA10_P
FMC_HPC0_LA08_N
FMC_HPC0_LA08_P
FMC_HPC0_LA00_CC_N
FMC_HPC0_LA00_CC_P
FMC_HPC0_CLK0_M2C_P
FMC_HPC0_CLK0_M2C_N
FMC_HPC0_LA13_N
FMC_HPC0_LA13_P
FMC_HPC0_LA14_N
FMC_HPC0_LA14_P
FMC_HPC0_LA15_P
FMC_HPC0_LA15_N
FMC_HPC0_LA16_N
FMC_HPC0_LA16_P
FMC_HPC0_LA12_N
FMC_HPC0_LA12_P
NC
NC
NC
NC
FMC_HPC0_LA19_P
FMC_HPC0_LA19_N
FMC_HPC0_LA01_CC_N
FMC_HPC0_LA01_CC_P
FMC_HPC0_LA11_P
FMC_HPC0_LA11_N
FMC_HPC0_LA18_CC_P
FMC_HPC0_LA18_CC_N
FMC_HPC0_LA17_CC_N
FMC_HPC0_LA17_CC_P
VCCO_64_AD22
VCCO_64_AB18
VCCO_64_AA21
VREF_64_W18
IO_L1P_T0L_N0_DBC_64_AE25
IO_L1N_T0L_N1_DBC_64_AE26
IO_L2P_T0L_N2_64_AB25
IO_L2N_T0L_N3_64_AB26
IO_L3P_T0L_N4_AD15P_64_AF24
IO_L3N_T0L_N5_AD15N_64_AF25
IO_L4P_T0U_N6_DBC_AD7P_64_AC26
IO_L4N_T0U_N7_DBC_AD7N_64_AD26
IO_L5P_T0U_N8_AD14P_64_AD24
IO_L5N_T0U_N9_AD14N_64_AD25
IO_L6P_T0U_N10_AD6P_64_AB24
IO_L6N_T0U_N11_AD6N_64_AC24
IO_T0U_N12_VRP_64_AF23
IO_L7P_T1L_N0_QBC_AD13P_64_AE22
IO_L7N_T1L_N1_QBC_AD13N_64_AF22
IO_L8P_T1L_N2_AD5P_64_AD23
IO_L8N_T1L_N3_AD5N_64_AE23
IO_L9P_T1L_N4_AD12P_64_AC22
IO_L9N_T1L_N5_AD12N_64_AC23
IO_L10P_T1U_N6_QBC_AD4P_64_AA22
IO_L10N_T1U_N7_QBC_AD4N_64_AB22
IO_L11P_T1U_N8_GC_64_AD21
IO_L11N_T1U_N9_GC_64_AE21
IO_L12P_T1U_N10_GC_64_AB21
IO_L12N_T1U_N11_GC_64_AC21
IO_T1U_N12_64_AF20
IO_L13P_T2L_N0_GC_QBC_64_AD20
IO_L13N_T2L_N1_GC_QBC_64_AE20
IO_L14P_T2L_N2_GC_64_AC19
IO_L14N_T2L_N3_GC_64_AD19
IO_L15P_T2L_N4_AD11P_64_AF18
IO_L15N_T2L_N5_AD11N_64_AF19
IO_L16P_T2U_N6_QBC_AD3P_64_AC18
IO_L16N_T2U_N7_QBC_AD3N_64_AD18
IO_L17P_T2U_N8_AD10P_64_AE17
IO_L17N_T2U_N9_AD10N_64_AF17
IO_L18P_T2U_N10_AD2P_64_AD16
IO_L18N_T2U_N11_AD2N_64_AE16
IO_T2U_N12_64_AE18
IO_L19P_T3L_N0_DBC_AD9P_64_Y20
IO_L19N_T3L_N1_DBC_AD9N_64_Y21
IO_L20P_T3L_N2_AD1P_64_AA19
IO_L20N_T3L_N3_AD1N_64_AB19
IO_L21P_T3L_N4_AD8P_64_AA20
IO_L21N_T3L_N5_AD8N_64_AB20
IO_L22P_T3U_N6_DBC_AD0P_64_AB17
IO_L22N_T3U_N7_DBC_AD0N_64_AC17
IO_L23P_T3U_N8_64_Y17
IO_L23N_T3U_N9_64_AA17
IO_L24P_T3U_N10_64_Y18
IO_L24N_T3U_N11_64_AA18
IO_T3U_N12_64_AC16
XCKU5PFFVB676
BANK 64
U1
AC16
AA18
Y18
AA17
Y17
AC17
AB17
AB20
AA20
AB19
AA19
Y21
Y20
AE18
AE16
AD16
AF17
AE17
AD18
AC18
AF19
AF18
AD19
AC19
AE20
AD20
AF20
AC21
AB21
AE21
AD21
AB22
AA22
AC23
AC22
AE23
AD23
AF22
AE22
AF23
AC24
AB24
AD25
AD24
AD26
AC26
AF25
AF24
AB26
AB25
AE26
AE25
W18
AA21
AB18
AD22
SOC_676_1MM_IRON
SOC_DK5_FFVB676_IRONWOOD
FMC_HPC0_LA20_P
FMC_HPC0_LA20_N
FMC_HPC0_LA21_N
FMC_HPC0_LA21_P
FMC_HPC0_LA22_P
FMC_HPC0_LA22_N
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- wx0261262020-09-17资源很好,谢谢分享,
- luohuajiexiejuan2019-01-16不错的资源,感谢,有用

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