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RK3288 TRM

FuZhou Rockchip Electronics Co.,Ltd. 1498

Chapter 42 Serial Peripheral Interface (SPI)

42.1 Overview

The serial peripheral interface is an APB slave device. A four wire full duplex serial protocol

from Motorola. There are four possible combinations for the serial clock phase and polarity.

The clock phase (SCPH) determines whether the serial transfer begins with the falling edge of

slave select signals or the first edge of the serial clock. The slave select line is held high when

the SPI is idle or disabled. This SPI controller can work as either master or slave mode.

SPI Controller supports the following features:

 Support Motorola SPI, TI Synchronous Serial Protocol and National Semiconductor

Microwire interface

 Support 32-bit APB bus

 Support two internal 16-bit wide and 32-location deep FIFOs, one for transmitting and

the other for receiving serial data

 Support two chip select signals in master mode

 Support 4, 8, 16 bit serial data transfer

 Support configurable interrupt polarity

 Support asynchronous APB bus and SPI clock

 Support master and slave mode

 Support DMA handshake interface and configurable DMA water level

 Support transmit FIFO empty, underflow, receive FIFO full, overflow, interrupt and all

interrupts can be masked

 Support configurable water level of transmit FIFO empty and receive FIFO full interrupt

 Support combine interrupt output

 Support up to half of SPI clock frequency transfer in master mode and one sixth of SPI

clock frequency transfer in slave mode

 Support full and half duplex mode transfer

 Stop transmitting SCLK if transmit FIFO is empty or receive FIFO is full in master mode

 Support configurable delay from chip select active to SCLK active in master mode

 Support configurable period of chip select inactive between two parallel data in master

mode

 Support big and little endian, MSB and LSB first transfer

 Support two 8-bit audio data store together in one 16-bit wide location

 Support sample RXD 0~3 SPI clock cycles later

 Support configurable SCLK polarity and phase

 Support fix and incremental address access to transmit and receive FIFO

42.2 Block Diagram

The SPI Controller comprises with:

 AMBA APB interface and DMA Controller Interface

 Transmit and receive FIFO controllers and an FSM controller

 Register block

 Shift control and interrupt

T-chip Only

RK3288 TRM

FuZhou Rockchip Electronics Co.,Ltd. 1500

42.3 Function description

SPI Master SPI Slave

clk

txd

rxd

clk

txd

rxd

Fig. 42-2 SPI Master and Slave Interconnection

The SPI controller support dynamic switching between master and slave in a system. The

diagram show how the SPI controller connects with other SPI devices.

Operation Modes

The SPI can be configured in the following two fundamental modes of operation: Master Mode

when SPI_CTRLR0 [20] is 1’b0, Slave Mode when SPI_CTRLR0 [20] is 1’b1.

Transfer Modes

The SPI operates in the following three modes when transferring data on the serial bus.

1. Transmit and Receive

When SPI_CTRLR0 [19:18] == 2‘b00, both transmit and receive logic are valid.

2. Transmit Only

When SPI_CTRLR0 [19:18] == 2‘b01, the receive data are invalid and should not be stored in

the receive FIFO.

3. Receive Only

When SPI_CTRLR0 [19:18] == 2‘b10, the transmit data are invalid.

Clock Ratios

A summary of the frequency ratio restrictions between the bit-rate clock (sclk_out / sclk_in)

and the SPI peripheral clock (spi_clk) are described as,

When SPI Controller works as master, the F

spi_clk

>= 2 × (maximum F

sclk_out

)

When SPI Controller works as slave, the F

spi_clk

>= 6 × (maximum F

sclk_in

)

With the SPI, the clock polarity (SCPOL) configuration parameter determines whether the

inactive state of the serial clock is high or low. To transmit data, both SPI peripherals must

have identical serial clock phase (SCPH) and clock polarity (SCPOL) values. The data frame

can be 4/8/16 bits in length.

When the configuration parameter SCPH = 0, data transmission begins on the falling edge of

the slave select signal. The first data bit is captured by the master and slave peripherals on the

first edge of the serial clock; therefore, valid data must be present on the txd and rxd lines

prior to the first serial clock edge. The following two figures show a timing diagram for a single

SPI data transfer with SCPH = 0. The serial clock is shown for configuration parameters SCPOL

= 0 and SCPOL = 1.

T-chip Only

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