TIPDcontrollerTPS65982_PDController资源-CSDN下载

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### TI PD Controller TPS65982：Type C PD Controller #### 一、产品概述 TPS65982是一款独立的USB Type-C与USB Power Delivery (PD)控制器，能够提供电缆插头方向检测及配置功能，适用于主机（源）、设备（接收端）或主机-设备模式下的应用。在电缆插入时，该控制器能够通过CC线利用USB PD协议进行通信，并在完成电缆检测和USB PD协商后，自动启用适当的电源路径并配置内部和可选外部多路复用器。 #### 二、主要特性 1. **USB PD 控制器**：TPS65982作为一个完整的USB PD控制器，支持电缆插头方向检测以及主机、设备或双角色模式下的配置。 2. **Bi-Phase Marked Encoding/Decoding (BMC)**：能够利用BMC进行编码和解码，在CC线上执行USB PD协议通信。 3. **物理层(PHY)协议支持**：符合USB PD的物理层规范，确保通信过程中的数据完整性。 4. **策略引擎**：内置策略引擎支持启动时和主机控制下的配置选项。 5. **USB Type-C规格兼容**：符合最新的USB Type-C规范，支持自动检测USB电缆插头的连接状态和方向。 6. **功率路径管理**：自动管理适当的功率路径，确保设备根据协商结果正确供电。 7. **多路复用器配置**：能够配置内部和外部多路复用器，支持不同的工作模式设置。 8. **电源开关**：内置的端口电源开关支持最高3A电流，适用于为传统和USB Type-C设备供电。 9. **双向电源路径**：支持高达20V电压的3A电流，可以作为主机、设备或主机-设备模式下使用。 10. **过流保护与过压保护**：具备过流保护和过压保护功能，确保系统的稳定性和安全性。 #### 三、详细说明 - **USB Type-C和USB PD标准**：TPS65982完全遵循USB Type-C和USB PD标准，能够支持多种工作模式，包括默认的500mA电流、1.5A电流和3A电流。 - **电缆检测与方向识别**：通过CC引脚上的混合信号前端，TPS65982能够检测到USB Type-C电缆的插入事件，并自动确定其连接方向。 - **通信与协议支持**：采用BMC编码方式，在CC线上执行USB PD协议，确保了数据的有效传输。 - **策略配置与控制**：支持启动时配置和主机控制下的配置选项，增强了灵活性和可定制性。 - **功率路径管理**：根据电缆检测结果和USB PD协商结果，自动启用相应的电源路径。 - **多路复用器配置**：支持对内部和外部多路复用器的配置，以适应不同的应用场景。 - **端口电源开关**：内置的5V 3A电源开关用于支持传统和USB Type-C设备的供电需求。 - **双向电源转换**：提供了一个5V至20V、最大3A的双向电源转换路径，可以作为主机或设备使用。 - **过流与过压保护**：内置的过流限流器和过压保护器确保系统的安全性和可靠性。 #### 四、应用领域 TPS65982非常适合应用于各种USB Type-C设备，如笔记本电脑、平板电脑、智能手机等，尤其适用于那些需要高性能充电和数据传输功能的应用场景。 TPS65982是一款高度集成的USB Type-C和USB PD控制器，具有强大的功能和灵活的配置选项，是实现USB Type-C设备高效管理和优化的理想选择。

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Host

Interface

High

Speed

Mux

SEL

External FET Sense and CTRL

Alternate Mode Mux Ctrl

TPS65982

POL

D+/-

SBU1 /2

CC/V

CONN

BUS

GND

CC1/2

USB_TP/TN

USB_BP /BN

SBU1/2

3 A

SuperSpeed Mux

3.3 V

5-20 V

5 A

5-20 V

5 V

Type-C Cable Detection

and

USB PD Controller

USB

Type-C

Connector

USB2.0

Sideband-Use

Data

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

TPS65982

SLVSD02A –MARCH 2015–REVISED JUNE 2015

TPS65982 USB Type-C and USB PD Controller, Power Switch, and High Speed Multiplexer

1 Features 3 Description

The TPS65982 is a stand-alone USB Type-C &

• USB Power Delivery (PD) Controller

Power Delivery (PD) controller providing cable plug

– Mode Configuration for Source (Host), Sink

and orientation detection at the USB Type-C

(Device), or Source-Sink

connector. Upon cable detection, the TPS65982

– Bi-Phase Marked Encoding/Decoding (BMC)

communicates on the CC wire using the USB PD

protocol. When cable detection and USB PD

– Physical Layer (PHY) Protocol

negotiation are complete, the TPS65982 enables the

– Policy Engine

appropriate power path and configures alternate

– Configurable at Boot and Host-Controlled

mode settings for internal and (optional) external

multiplexers.

• USB Type-C Specification Compliant

– Detect USB Cable Plug Attach

The mixed-signal front end on the CC pins advertises

default (500 mA), 1.5 A or 3 A for Type-C power

– Cable Orientation and Role Detection

sources, detects a plug event and determines the

– Assign CC and VCONN Pins

USB Type-C cable orientation, and autonomously

– Advertise Default, 1.5 A or 3 A for Type-C

negotiates USB PD contracts by adhering to the

Power

specified bi-phase marked coding (BMC) and

physical layer (PHY) protocol.

• Port Power Switch

The port power switch provides up to 3 A

– 5-V, 3-A Switch to VBUS for Type-C Power

downstream at 5 V for legacy and Type-C USB

– 5-V to 20-V, 3-A Bidirectional Switch to or from

power. An additional bi-directional switch path

VBUS for USB PD Power

provides USB PD power up to 3 A at a maximum of

– 5-V, 600-mA Switches for VCONN

20 V as either a source (host), sink (device), or

source-sink.

– Over-Current Limiter, Overvoltage Protector

– Slew Rate Control

The TPS65982 is also an Upstream-Facing Port

(UFP), Downstream-Facing Port (DFP), or Dual-Role

– Hard Reset Support

Port for data. The port data multiplexer passes data

• Port Data Multiplexer

to or from the top or bottom D+/D– signal pair at the

– USB 2.0 HS Data, UART Data, and Low

port for USB 2.0 HS and has a USB 2.0 Low Speed

Speed Endpoint

Endpoint. Additionally, the Sideband-Use (SBU)

signal pair is used for auxiliary or Alternate Modes of

– Sideband Use Data for Alternate Modes

communication (DisplayPort or Thunderbolt™, for

(DisplayPort and Thunderbolt™)

example).

• Power Management

The power management circuitry utilizes a 3.3 V

– Gate Control and Current Sense for External

inside the system and also uses VBUS to start up

5-V to 20-V, 5-A Bi-directional Switch (Back-to-

and negotiate power for a dead-battery or no-battery

Back NFETs)

condition.

– Power Supply from 3.3-V or VBUS Source

Device Information

(1)

– 3.3-V LDO Output for Dead Battery Support

PART NUMBER PACKAGE BODY SIZE (NOM)

• BGA MicroStar Junior Package

TPS65982 BGA (96) 6.00 mm x 6.00 mm

– 0.5-mm Pitch

(1) For all available packages, see the orderable addendum at

– Through-Hole Via Compatible for All Pins

the end of the data sheet.

2 Applications

• Notebook Computers

• Tablets and Ultrabooks

• Docking Systems

• Charger Adapters

• USB PD Hosts, Devices, and Dual-Role Ports

• USB PD-Enabled Bus-Powered Devices

• DisplayPort, Thunderbolt™ and HDMI

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS65982

SLVSD02A –MARCH 2015–REVISED JUNE 2015

www.ti.com

Table of Contents

6.21 SPI Master Characteristics ................................... 22

1 Features.................................................................. 1

6.22 Single-Wire Debugger (SWD) Timing

2 Applications ........................................................... 1

Requirements........................................................... 22

3 Description ............................................................. 1

6.23 BUSPOWERZ Configuration Requirements ......... 23

4 Revision History..................................................... 2

6.24 HPD Timing Requirements and Characteristics ... 23

5 Pin Configuration and Functions......................... 3

6.25 Thermal Shutdown Characteristics ....................... 23

6 Specifications......................................................... 7

6.26 Oscillator Requirements and Characteristics........ 23

6.1 Absolute Maximum Ratings ...................................... 7

6.27 Typical Characteristics.......................................... 24

6.2 ESD Ratings.............................................................. 7

7 Parameter Measurement Information ................ 25

6.3 Recommended Operating Conditions....................... 8

8 Detailed Description ............................................ 28

6.4 Thermal Information.................................................. 8

8.1 Overview ................................................................. 28

6.5 Power Supply Requirements and Characteristics..... 9

8.2 Functional Block Diagram ....................................... 29

6.6 Power Supervisor Characteristics........................... 10

8.3 Feature Description................................................. 29

6.7 Power Consumption Characteristics....................... 10

8.4 Device Functional Modes........................................ 66

6.8 Cable Detection Characteristics.............................. 11

8.5 Programming .......................................................... 73

6.9 USB-PD Baseband Signal Requirements and

9 Application and Implementation ........................ 78

Characteristics ......................................................... 12

9.1 Application Information............................................ 78

6.10 USB-PD TX Driver Voltage Adjustment

9.2 Typical Application .................................................. 78

Parameter ................................................................ 12

6.11 Port Power Switch Characteristics........................ 13

10 Power Supply Recommendations ..................... 88

6.12 Port Data Multiplexer Switching and Timing

10.1 3.3 V Power .......................................................... 88

Characteristics ......................................................... 16

10.2 1.8 V Core Power.................................................. 88

6.13 Port Data Multiplexer Clamp Characteristics ........ 18

10.3 VDDIO................................................................... 88

6.14 Port Data Multiplexer SBU Detection

11 Layout................................................................... 90

Requirements........................................................... 18

11.1 Layout Guidelines ................................................. 90

6.15 Port Data Multiplexer Signal Monitoring Pull-Up and

11.2 Layout Example .................................................... 93

Pull-Down Characteristics........................................ 18

12 Device and Documentation Support ............... 108

6.16 Port Data Multiplexer USB Endpoint Requirements

12.1 Device Support.................................................... 108

and Characteristics .................................................. 18

12.2 Documentation Support ...................................... 108

6.17 Port Data Multiplexer BC1.2 Detection

Requirements and Characteristics........................... 19

12.3 Community Resources........................................ 108

6.18 Analog-to-Digital Converter (ADC)

12.4 Trademarks......................................................... 108

Characteristics ......................................................... 19

12.5 Electrostatic Discharge Caution.......................... 108

6.19 Input/Output (I/O) Requirements and

12.6 Glossary.............................................................. 108

Characteristics ......................................................... 19

13 Mechanical, Packaging, and Orderable

6.20 I

C Slave Requirements and Characteristics........ 21

Information ......................................................... 108

4 Revision History

Changes from Original (March 2015) to Revision A Page

• Initial release of Production Datasheet................................................................................................................................... 1

Product Folder Links: TPS65982

TPS65982

SLVSD02A –MARCH 2015–REVISED JUNE 2015

www.ti.com

Pin Functions (continued)

POR

I/O DESCRIPTION

STATE

NAME NO.

LOW CURRENT POWER PINS

VIN_3V3 H1 Power NA Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.

VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO instead of

VDDIO B1 Power NA LDO_3V3. When VDDIO is not used, tie pin to LDO_3V3. When not tied to LDO_3V3

and used as a supply input, bypass with capacitance CVDDIO to GND.

Output of supply switched from VIN_3V3. Bypass with capacitance COUT_3V3 to

VOUT_3V3 H2 Power NA

GND. Float pin when unused.

Output of the VBUS to 3.3 V LDO or connected to VIN_3V3 by a switch. Main

LDO_3V3 G1 Power NA internal supply rail. Used to power external flash memory. Bypass with capacitance

CLDO_3V3 to GND.

Output of the 3.3 V or 1.8 V LDO for Core Analog Circuits. Bypass with capacitance

LDO_1V8A K1 Power NA

CLDO_1V8A to GND.

Output of the 3.3 V or 1.8 V LDO for Core Digital Circuits. Bypass with capacitance

LDO_1V8D A2 Power NA

CLDO_1V8D to GND.

Output of the USB-PD BMC transceiver output level LDO. Bypass with capacitance

LDO_BMC E1 Power NA

CLDO_BMC to GND.

TYPE-C PORT PINS

C_CC1 L9 Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC1 to GND.

C_CC2 L10 Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC2 to GND.

Tie pin to C_CC1 when configured to receive power in dead-battery or no-power

RPD_G1 K9 Analog I/O Hi-Z

condition. Tie pin to GND otherwise.

Tie pin to C_CC2 when configured to receive power in dead-battery or no-power

RPD_G2 K10 Analog I/O Hi-Z

condition. Tie pin to GND otherwise.

C_USB_TP K6 Analog I/O Hi-Z Port side Top USB D+ connection to Port Multiplexer.

C_USB_TN L6 Analog I/O Hi-Z Port side Top USB D- connection to Port Multiplexer.

C_USB_BP K7 Analog I/O Hi-Z Port side Bottom USB D+ connection to Port Multiplexer.

C_USB_BN L7 Analog I/O Hi-Z Port side Bottom USB D- connection to Port Multiplexer.

C_SBU1 K8 Analog I/O Hi-Z Port side Sideband Use connection of Port Multiplexer.

C_SBU2 L8 Analog I/O Hi-Z Port side Sideband Use connection of Port Multiplexer.

PORT MULTIPLEXER PINS

Resistive Pull

SWD_DATA F4 Digital I/O SWD serial data. Float pin when unused.

High

Resistive Pull

SWD_CLK G4 Digital Input SWD serial clock. Float pin when unused.

High

UART serial receive data. Connect pin to another TPS65982 UART_TX to share

UART_RX F2 Digital Input Digital Input firmware. Connect UART_RX to UART_TX when not connected to another

TPS65982 and ground pin through a 100 kΩ resistance.

UART serial transmit data. Connect pin to another TPS65982 UART_TX to share

UART_TX E2 Digital Output UART_RX firmware. Connect UART_RX to UART_TX when not connected to another

TPS65982.

System side USB2.0 high-speed connection to Port Multiplexer. Ground pin with

USB_RP_P L5 Analog I/O Hi-Z

between 1 kΩ and 5 MΩ resistance when unused.

System side USB2.0 high-speed connection to Port Multiplexer. Ground pin with

USB_RP_N K5 Analog I/O Hi-Z

between 1 kΩ and 5 MΩ resistance when unused.

System side low speed TX from system to port. This pin is configurable to be an

LSX_R2P L4 Digital Input Digital Input input to the digital core or the crossbar multiplexer to the port. Ground pin with

between 1 kΩ and 5 MΩ resistance when unused.

System side low speed RX to system from port. This pin is configurable to be an

LSX_P2R K4 Digital Output Hi-Z output from the digital core or the crossbar multiplexer from the port. Float pin when

unused.

System side DisplayPort connection to Port Multiplexer. Ground pin with between 1

AUX_P J1 Analog I/O Hi-Z

kΩ and 5 MΩ resistance when unused.

System side DisplayPort connection to Port Multiplexer. Ground pin with between 1

AUX_N J2 Analog I/O Hi-Z

kΩ and 5 MΩ resistance when unused.

Product Folder Links: TPS65982

TPS65982

www.ti.com

SLVSD02A –MARCH 2015–REVISED JUNE 2015

Pin Functions (continued)

POR

I/O DESCRIPTION

STATE

NAME NO.

EXTERNAL HV FET CONTROL/SENSE PINS AND SOFT START

Positive sense for external high voltage power path current sense resistance. Short

SENSEP B10 Analog Input Analog Input

pin to VBUS when unused.

Positive sense for external high voltage power path current sense resistance. Short

SENSEN A10 Analog Input Analog Input

pin to VBUS when unused.

Analog Short to

HV_GATE1 B9 External NFET gate control for high voltage power path. Float pin when unused.

Output SENSEP

Analog

HV_GATE2 A9 Short to VBUS External NFET gate control for high voltage power path. Float pin when unused.

Output

Analog

SS H7 Driven Low Soft Start. Tie pin to capacitance CSS to ground.

Output

DIGITAL CORE I/O AND CONTROL PINS

External resistance setting for oscillator accuracy. Connect R_OSC to GND through

R_OSC G2 Analog I/O Hi-Z

resistance RR_OSC.

General Purpose Digital I/O 0. Alternate mode select signal to external Super Speed

GPIO0

B2 Digital I/O Hi-Z multiplexer (tri-state capable with pull-up and pull-down resistors). Ground pin with a

(HD3 AMSEL)

1-MΩ resistor when unused in the application.

GPIO1

General Purpose Digital I/O 1. Must be tied high or low through a 1 kΩ pull-up or

C2 Digital I/O Hi-Z

pull-down resistor when used as a configuration input.

(CONFIG0)

General Purpose Digital I/O 2. Float pin if it is configured as a push-pull output in the

GPIO2 D10 Digital I/O Hi-Z

application. Ground pin with a 1-MΩ resistor when unused in the application.

General Purpose Digital I/O 3. Enable signal to external Super Speed multiplexer.

GPIO3

G11 Digital I/O Hi-Z Float pin if it is configured as a push-pull output in the application. Ground pin with a

(HD3 EN)

1-MΩ resistor when unused in the application.

General Purpose Digital I/O 4. Configured as Hot Plug Detect (HPD) TX and/or HPD

GPIO4

C10 Digital I/O Hi-Z RX when DisplayPort Mode supported. Ground pin with a 1-MΩ resistor when

(HPD TXRX)

unused in the application.

General Purpose Digital I/O 5. Can be configured as Hot Plug Detect (HPD) RX

GPIO5

when DisplayPort Mode supported. Must be tied high or low through a 1 kΩ pull-up

E10 Digital I/O Hi-Z

or pull-down resistor when used as a configuration input. Ground pin with a 1 MΩ

(HPD RX)

resistor when unused in the application.

General Purpose Digital I/O 6. Float pin if it is configured as a push-pull output in the

GPIO6 G10 Digital I/O Hi-Z

application. Ground pin with a 1-MΩ resistor when unused in the application.

General Purpose Digital I/O 7. Float pin if it is configured as a push-pull output in the

GPIO7 D7 Digital I/O Hi-Z

application. Ground pin with a 1-MΩ resistor when unused in the application.

General Purpose Digital I/O 8. Float pin if it is configured as a push-pull output in the

GPIO8 H6 Digital I/O Hi-Z

application. Ground pin with a 1-MΩ resistor when unused in the application.

RESETZ

Push-Pull General Purpose Digital I/O 9. Active low reset output when VOUT_3V3 is low

F11 Digital I/O

Output (Low) (driven low on start-up). Float pin when unused.

(GPIO9)

General Purpose Digital I/O 10. Sampled by ADC at boot. Tie pin to LDO_3V3

BUSPOWERZ

through a 100-kΩ resistor to disable PP_HV and PP_EXT power paths during dead-

F10 Analog Input Input (Hi-Z)

battery or no-battery boot conditions. Refer to the BUSPOWERZ table for more

(GPIO10)

details.

General Purpose Digital I/O 11. Forces RESETZ to assert. By default, this pin

MRESET

E11 Digital I/O Hi-Z asserts RESETZ when pulled high. The pin can be programmed to assert RESETZ

(GPIO11)

when pulled low. Ground pin with a 1MΩ resistor when unused in the application.

DEBUG4

General Purpose Digital I/O 12. Must be tied high or low through a 1-kΩ pull-up or

K3 Digital I/O Hi-Z

(GPIO12,

pull-down resistor when used as a configuration input.

CONFIG2)

DEBUG3

General Purpose Digital I/O 13. Must be tied high or low through a 1-kΩ pull-up or

L3 Digital I/O Hi-Z

(GPIO13,

pull-down resistor when used as a configuration input.

CONFIG1)

DEBUG2

General Purpose Digital I/O 14. Polarity signal to external Super Speed multiplexer.

K2 Digital I/O Hi-Z Float pin if it is configured as a push-pull output in the application. Ground pin with a

(GPIO14, HD3

1-MΩ resistor when unused in the application.

POL)

DEBUG1

General Purpose Digital I/O 15. Ground pin with a 1-MΩ resistor when unused in the

L2 Digital I/O Hi-Z

application.

(GPIO15)

DEBUG_CTL1

General Purpose Digital I/O 16. At power-up, pin state is sensed to determine bit 4 of

E4 Digital I/O Hi-Z

(GPIO16, I

the I

C address.

ADDR B4)

Product Folder Links: TPS65982

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