risc-v core Verilog源码

E51 Coreplex IP Evaluation RTL Notes Release: v1p0 Date: 05/04/2017 This version of E51 Coreplex IP is meant for evaluation purposes only. As such, the RTL source code has been intentionally obfuscated, and its use is governed by your Evaluation License. There may be other functional limitations as described in the Evaluation RTL User Guide. The full version of E51 Coreplex IP will not have these restrictions. RTL contents: + One E51 core (RV64IMAC) Changes from last release: N/A Top-level synthesizable module name: E51_ECoreplexIP_system Top-level ports: ============================================================= | Function | Signal name | Width | ============================================================= | Reset | reset | | | Periphery clock | clock | | | Core clock | io_coreClock | | | Realtime clock | io_rtcToggle | | | Debug Module Interface | io_jtag_* | | | Debugger-driven Reset | io_ndreset | | | Debug Active Indicator | io_dmactive | | | Reset vector address | io_resetVector | 32b | | Global Interrupts | io_global_interrupts | 511b | | Local Interrupts | io_local_interrupts_0 | 16b | | Connect TL-UL slaves | io_periph_port_tl_0_* | 32b | ============================================================= Clocking restrictions: - io_coreClock and clock must have rates that divide rationally. - io_coreClock rate must be equal to or higher than the periphery clock rate. - io_local_interrupts_0 must be synchronized to io_coreClock. - io_global_interrupts must be synchronized to clock. - reset must be synchronized to clock. - Please see the Evaluation RTL User Guide for additional information.