异步FIFO源程序

module yibufifo1 (rdata, wfull, rempty, wdata, winc, wclken, wclk, wrst_n, rinc, rclk, rrst_n);

parameter DATASIZE = 10; // Memory data word width

parameter ADDRSIZE = 4; // Number of memory address bits

parameter DEPTH = 1<<ADDRSIZE; // DEPTH = 2**ADDRSIZE

parameter N = ADDRSIZE-1;

output [DATASIZE-1:0] rdata;

output wfull;

output rempty;

input [DATASIZE-1:0] wdata;

input winc, wclken, wclk, wrst_n;

input rinc, rclk, rrst_n;

reg [ADDRSIZE-1:0] wptr, rptr;

wire [ADDRSIZE-1:0] waddr, raddr;

wire aempty_n, afull_n;

reg direction;

reg [ADDRSIZE-1:0] wbin, rbin;

reg rempty, rempty2;

wire [ADDRSIZE-1:0] rgnext, rbnext;

reg wfull, wfull2;

wire [ADDRSIZE-1:0] wgnext, wbnext;

wire high = 1'b1;
  
wire dirset_n = ~( (wptr[N]^rptr[N-1]) & ~(wptr[N-1]^rptr[N]));

wire dirclr_n = ~((~(wptr[N]^rptr[N-1]) & (wptr[N-1]^rptr[N]))|~wrst_n);

//--------------------------

//comp 

//--------------------------

always @(posedge high or negedge dirset_n or negedge dirclr_n)

if (!dirclr_n)

    direction <= 1'b0;

else if (!dirset_n)