Zynq-7000 SoC Technical Reference Manual www.xilinx.com 4
UG585 (v1.12.2) July 1, 2018
03/07/2013 1.5 Added 7z100 device and made minor clarifications to Chapter 1, Introduction. Made
minor clarifications to Chapter 2, Signals, Interfaces, and Pins, Chapter 3, Application
Processing Unit, Chapter 4, System Addresses, and Chapter 5, Interconnect. Clarified
section 6.1 Introduction and other sections, and added PS Independent JTAG
Non-Secure Boot section in Chapter 6, Boot and Configuration. Made minor
clarifications to Chapter 7, Interrupts, Chapter 8, Timers, Chapter 9, DMA Controller,
Chapter 10, DDR Memory Controller, Chapter 11, Static Memory Controller, and
Chapter 12, Quad-SPI Flash Controller. Expanded 12.2 Functional Description in
Chapter 12, Quad-SPI Flash Controller. Made minor clarifications to Chapter 13,
SD/SDIO Controller. Made major clarifications/updates to Chapter 14, General Purpose
I/O (GPIO). Reworked and expanded Chapter 15, USB Host, Device, and OTG Controller.
Made minor clarifications to Chapter 16, Gigabit Ethernet Controller. Reworked and
expanded Chapter 17, SPI Controller. Made minor clarifications to Chapter 18, CAN
Controller, and Chapter 19, UART Controller. Made major clarifications/updates to
Chapter 20, I2C Controller (added new sections, 20.3 Programmer’s Guide, 20.4 System
Functions, and 20.5 I/O Interface). Made minor clarifications to Chapter 21,
Programmable Logic Description and added new sections 21.1.2 PL Resources by Device
Type and 21.1.3 Notices. Made minor clarifications to Chapter 22, Programmable Logic
Design Guide and Chapter 23, Programmable Logic Test and Debug. Reworked and
expanded Chapter 24, Power Management. Made minor clarifications to Chapter 25,
Clocks, Chapter 26, Reset System, Chapter 27, JTAG and DAP Subsystem, Chapter 28,
System Test and Debug, and Chapter 29, On-Chip Memory (OCM). Reworked and
expanded Chapter 30, XADC Interface. Made minor clarifications to
Chapter 31, PCI
Express. Reworked and expanded Chapter 32, Device Secure Boot. Updated Appendix A,
Additional Resources. Updated register database in sections B.3 Module Summary
through B.34 USB Controller (usb) in Appendix B.
06/28/2013 1.6 Added icons where applicable. Enhanced first sentence under Quad-SPI Controller in c.
Clarified first paragraph, added step 2, and clarified step 5 in section 2.4 PS–PL Voltage
Level Shifter Enables. Changed “drive strength” to “slew rate” in section 2.5.7 MIO Pin
Electrical Parameters. Added second sentence and updated Table 2- 1 1 in section
2.7.4 Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals. Corrected Note 4 in Tab l e 4-1
and Tab le 4- 2 . Made minor clarifications and added new RSA Authentication Time
section to Chapter 6, Boot and Configuration. Made minor clarifications to sections
7.2.2 CPU Private Peripheral Interrupts (PPI) and 7.2.3 Shared Peripheral Interrupts
(SPI), and updated Table 7- 4 and Ta b l e 7-5. Clarified first row in Table 9- 1 2. Added tip
to section 10.4.3 Aging Counter, added sentence to Write Leveling, and step 2 in section
10.9.2 Changing Clock Frequencies, and moved section 10.9.6 DDR Power Reduction
from Chapter 24, Power Management to this chapter. Added tip to section
11.2.2 Clocks. Added Table 12-8. Added
MMC3.31 standard information to section
13.1 Introduction. Added step 6 to section 14.3.1 Start-up Sequence, added section
14.3.5 GPIO as Wake-up Event, added second paragraph to 14.4.1 Clocks. Added
section 16.7 Known Issues. Added note to 17.4.2 Clocks. Changed value of 107 Mb to
140 Mb in second sentence under section 21.4 Configuration. Added values for the
7z100 device in Table 21-2. Clarified first paragraph in section 24.2.2 PL Power-down
Control and updated Tabl e 24 - 2 . Added note to section 25.6.1 USB Clocks, clarified
second paragraph in section 25.10.4 PLLs, and added sentence to steps 2 and 3 in
Software-Controlled PLL Update section. Changed “RESET_REASON” to
“REBOOT_STATUS in section 26.2.3 System Software Reset, added section 26.5 Register
Overview, deleted first two rows from Ta b le 26-2 and modified last paragraph in section
26.5.1 Persistent Registers. Clarified section 29.1 Introduction, added three paragraphs
to Starvation Scenarios section, and added 29.2.5 Address Mapping heading. Corrected
spelling of “MCTRL” to “MCTL” in sections 30.4 Programming Guide for the PS-XADC
Interface and 30.7.2 Resets.
Date Version Revision
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