idma.zip_VDSP++5.0百度云_pleasantb4s

/* This Program demonstrates the IDMA port using Long write cycles. This Program can be tested using Loop back in EZ-KIT. To run this program in the EZ-KIT the following connections has to be made 1. D[8:10] is connected to IAD[0:2] 2. FL0 is connected to /IS 3. FL1 is connected to /IRD 4. FL2 is connected to /IWR 5. /IACK is connected to /IRQ2 Interrupt is generated when IDMA gives the asserts /IACK signal and in the ISR the /IS & /IWR signals are deasserted. This program writes the data in the array data[8] into the address DM[0x1000] through the IDMA port. */ #include"sysreg.h" #include"signal.h" # define IDMA_Control *(int *)0x3fe0 # define IDMA_Overlay *(int *)0x3fe7 # define System_control *(int *)0x3fff volatile int dm data[8]={1,2,3,4,5,6,7,0}; volatile int dm busy_flag; volatile int dm i,k; void IRQ2_serv(); void write_to_idma(); void wait_if_busy(); void set_busyflag(); main() { IDMA_Control=0x5000; // DM[0x1000] IDMA_Overlay=0x8000; System_control=0x0000; //Disable SPORT1 & for alternative config. sysreg_write(sysreg_ICNTL,0x04); // /IRQ2 sensitivity=Edge sysreg_write(sysreg_IMASK,0x0000); //Disable all Interrupts sysreg_write(sysreg_IFC,0x00ff); // Clear all the pending interrupts interrupt(SIGIRQ2,IRQ2_serv); // Interrupt handler for /IRQ2 // set the initial state of signals to asm("set FL0;"); // appropriate states. asm("set FL1;"); asm("set FL2;"); for(i=0;i<8;i++) { write_to_idma(); } } void write_to_idma() { wait_if_busy(); set_busyflag(); io_space_write(0xA,data[i]); asm("reset fl2;"); // Drive Low (Assert) on both /IS and /IWR asm("reset fl0;"); } void IRQ2_serv() { asm("set fl2;"); // Deassert both the /IS & /IWR asm("set fl0;"); // signals busy_flag=0; } void wait_if_busy() { if(busy_flag==1) { } } void set_busyflag() { busy_flag=1; }