bcd.zip_二进制转换BCD码

module b_to_bcd( clk, rst_n, binary, state_en, BCD ); parameter b_length = 8; parameter bcd_len = 12; parameter idle = 5'b00001; parameter shift = 5'b00010; parameter wait_judge = 5'b00100; parameter judge = 5'b01000; parameter add_3 = 5'b10000; input clk; input rst_n; input [b_length-1:0] binary; input state_en; output reg [bcd_len-1:0] BCD; reg [b_length-1:0] reg_binary; reg [3:0] bcd_b, bcd_t, bcd_h; reg [3:0] shift_time; reg [5:0] c_state, n_state; reg add3_en; reg change_done; //this is a three section kind of state code style always@(posedge clk or negedge rst_n) begin if(!rst_n) c_state <= idle; else c_state <= n_state; end //the second section always@(posedge clk or negedge rst_n) begin if(!rst_n) c_state <= idle; else case(n_state) idle:begin if((binary!=0)&&(state_en==1'b1)&&(change_done==0'b0)) n_state <= shift; else n_state <= idle; end shift: n_state <= wait_judge; wait_judge: begin if(change_done==1'b1) n_state <= idle; else n_state <= judge; end judge:begin if(add3_en) n_state <= add_3; else n_state <= shift; end add_3:begin n_state <= shift; end default: n_state <= idle; endcase end //the third section always@(posedge clk or negedge rst_n) begin if(!rst_n) begin shift_time <= 4'b0; change_done <= 1'b0; add3_en <= 1'b0; end else case(n_state) idle:begin shift_time <= b_length; reg_binary <= binary; bcd_h <= 4'b0; bcd_t <= 4'b0; bcd_b <= 4'b0; end shift:begin {bcd_h,bcd_t,bcd_b,reg_binary} <= {bcd_h,bcd_t,bcd_b,reg_binary}<<1; shift_time <= shift_time-1; if(shift_time==1) change_done <= 1'b1; else change_done <= 1'b0; end wait_judge:begin if((bcd_h>=4'd5)||(bcd_t>=4'd5)||(bcd_b>=4'd5)) add3_en <= 1; else add3_en <= 0; if(change_done==1) BCD <= {bcd_h,bcd_t,bcd_b}; end judge: add3_en <= 0; add_3: begin if(bcd_h>=4'd5) bcd_h <= bcd_h + 4'b0011; else bcd_h <= bcd_h; if(bcd_t>=4'd5) bcd_t <= bcd_t + 4'b0011; else bcd_t <= bcd_t; if(bcd_b>=4'd5) bcd_b <= bcd_b + 4'b0011; else bcd_b <= bcd_b; end default: begin change_done <= 1'b0; add3_en <= 1'b0; end endcase end endmodule