Make sure no zero-bitsize connections appear

[mpharrigan]

This adds additional assertions to qualtran.testing to make sure none of the Connection objects have zero bitsize. The presence of such registers/connections likely breaks assumptions used by the rest of the library. cc #1102

Originally, I was going to add asserts to the QDTypes themselves, but 1) they're used in several places other than defining registers that actually appear in a composite bloq causing "false positives" in the test 2) performing those assertions at QDType instantiation makes it impossible to get around; whereas this current change will only result in a failure if you're using qlt_testing.assert_valid_bloq_decomposition or its friends (or the bloq_autotester) so this PR probably has some false negatives still remaining.

[mpharrigan]

cc @NoureldinYosri found this in reviewing #1057

[mpharrigan]

@tanujkhattar test_select_swap_qrom results in zero-sized registers for the 3rd data example of [[1],[2],[3]]. Can you fix?

Qualtran/qualtran/bloqs/data_loading/qrom_base.py

Line 227 in e2c6b82

selection_bitsizes = tuple((s - 1).bit_length() for s in _data[0].shape)

[mpharrigan]

StatePreparationViaRotations

Qualtran/qualtran/bloqs/state_preparation/state_preparation_via_rotation.py

Line 160 in cf2044d

return bit_length(slen(self.state_coefficients) - 1)

passed as selection bitsize to PRGAViaPhaseGradient. I don't know if this should actually be zero and the selection register needs to be omitted or if we still use a selection bit to select 1 value

@tanujkhattar can you fix

[mpharrigan]

@tanujkhattar can you approve. Looks like the failures are indeed fixed :)