RISC-V Blog

Blog What's New

XuanTie Co-Processor Interface Solution: A Bridge to Efficient Collaborative Computing

Weitong Su, Alibaba DAMO Academy Co-processors are specialized units designed to assist the main processor…

anishaDecember 13, 2024

AI Blog

Enhancing the Future of AI/ML with Attached Matrix Extension

Zhao Jiang, Alibaba DAMO Academy In recent years, the rapid advancement of AI technologies, particularly…

anishaNovember 22, 2024

Blog

Meet Andrea Gallo, RVFA: A Senior IT Leader’s Career Pivot

Andrea Gallo, RVFA Vice President of Technology at RISC-V InternationalAfter decades of a highly successful,…

Camille CalichonNovember 20, 2024

Blog

Triton kernel performance on RISC-V CPU

Introduction to Triton Triton is an open-source, Python-based Domain-Specific Language (DSL) developed by OpenAI to…

anishaNovember 15, 2024

Blog

Stream Computing Provides Smart Community Services Based on RISC-V Computing Power and LLMs

By Deke Wang and David Chen, Stream Computing In the wave of digital transformation, the…

anishaNovember 8, 2024

Blog

Stream Computing RISC-V Matrix Extension Open Source Project Upgrades to Version 0.5, Supporting Vector+Matrix Implementation

By Fujie Fan and David Chen, Stream Computing Background: In order to solve the problem…

anishaNovember 7, 2024

Blog Security

Real-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoT

DOME Cybersecurity provides a flexible Software Development Kit (SDK) for connecting the PolarFire FPGA to…

anishaNovember 6, 2024

Blog

How to Share Your Work and See What Others Are Building On RISC-V

Hello RISC-V Community, We’ve heard your feedback! Many of you expressed an interest in seeing…

Camille CalichonNovember 4, 2024

Blog

RISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source Innovations

On October 17, the inaugural RISC-V Eco-system Development Forum, held as part of the Guangdong-Hong…

anishaOctober 29, 2024

Blog

Chile’s First Steps with RISC-V: Paving the Way for Technological Innovation

Chile is embarking on an exciting journey into the world of RISC-V. As the country…

rafaelOctober 11, 2024

Blog

RISC-V Summit North America 2024: Keynotes and Industry Tracks

The RISC-V Summit North America 2024 is a pivotal event for the RISC-V community, bringing…

anishaOctober 11, 2024

Blog

Don’t Miss Out: RISC-V Summit North America 2024 – Register Before Prices Increase!

The RISC-V Summit North America 2024 is fast approaching, and it's a must-attend event for…

anishaOctober 9, 2024

Blog

Towards Generic RISC-V TEE Ecosystem with Penglai and OP-TEE

By Erhu Feng (Shanghai Jiao Tong University), Qingyu Shang (Shanghai Jiao Tong University), Yu-Chien Lin…

anishaOctober 8, 2024

Blog

AI/ML Innovations at RISC-V Summit North America: A Track to Watch

Registration prices for RISC-V Summit North America 2024 increase after Oct 11. Register today to…

anishaOctober 8, 2024

Blog

Join Us for the RISC-V Hackathon at Summit North America 2024!

We’re excited to team up with our members Andes, Codasip, and Tactical Computing Laboratories to…

Camille CalichonOctober 1, 2024

Blog

RISC-V Processor Design – Free YouTube Course by Maven Silicon

In this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of…

anishaSeptember 27, 2024

Blog

Get Started With Real-Time Systems Using Microchip’s PolarFire® SoC FPGA and TASKING Debug and Analyze Tools

By: Matej Antonijevic (TASKING) Developers who have struggled with achieving real-time performance and security in…

anishaSeptember 27, 2024

Blog

Debugging of PolarFire® SoC FPGAs Made Easy with Lauterbach’s TRACE32® Tools

By: Frank Riemenschneider, Senior Marketing Engineer at Lauterbach GmbH Microchip's PolarFire® System-on-Chip Field-Programmable Gate Array…

anishaSeptember 27, 2024

Blog

Box64 Adds Initial Support for RISC-V Vector 1.0 (RVV) Extension, Achieves up to 300% Performance Boost, Code Now Open-Source and Merged Upstream

The Box64 RISC-V backend has implemented scalar instructions to emulate x86_64 vector extensions like MMX…

anishaSeptember 27, 2024

Blog

TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor

By Wenbo Yin, Vice President of IC Design, TetraMem Inc. Introduction The rapid proliferation of…

anishaSeptember 26, 2024

Blog

Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC

NX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation…

anishaSeptember 25, 2024

Blog

Leveraging a Passion for Logic into a RISC-V Career

The path to success for an IT career is often paved with curiosity, dedication and…

Camille CalichonSeptember 17, 2024

Blog

Advancing AI the Brazilian Way: Fostering Innovation Through Collaboration and Open Standards

Brazil is making significant strides in developing artificial intelligence (AI) infrastructure, focusing primarily on High-Performance…

RISC-V Community NewsSeptember 9, 2024

Blog

Hot Chips and Even Hotter Connections: RISC-V is Everywhere!

The weather might have been scorching, but the networking at Hot Chips was on fire!…

loriSeptember 6, 2024

Blog

Trailblazers: Board of Directors Software Award Winners 2024

Four software leaders were honored at RISC-V Summit Europe 2024 for their remarkable contributions to…

anishaSeptember 5, 2024

Blog

The latest from RISC-V International and community members.

About

Policies

Specification

Developers

Industries

Events

Members

Resources

Join RISC-V International

Becoming a member of RISC-V International allows companies and individuals to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs.